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[147.11.176.192]) by smtp.gmail.com with ESMTPSA id j13-20020a056a00130d00b004f1025a4361sm23122330pfu.202.2022.04.20.18.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 18:17:36 -0700 (PDT) From: Bin Meng To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza , David Gibson , Greg Kurz Subject: [PATCH v2] target/ppc: Fix BookE debug interrupt generation Date: Thu, 21 Apr 2022 09:17:29 +0800 Message-Id: <20220421011729.1148727-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Fabiano Rosas Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per E500 core reference manual [1], chapter 8.4.4 "Branch Taken Debug Event" and chapter 8.4.5 "Instruction Complete Debug Event": "A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT] are set ... Branch taken debug events are not recognized if MSR[DE] is cleared when the branch instruction executes." "An instruction complete debug event occurs when any instruction completes execution so long as MSR[DE] and DBCR0[ICMP] are both set ... Instruction complete debug events are not recognized if MSR[DE] is cleared at the time of the instruction execution." Current codes do not check MSR.DE bit before setting HFLAGS_SE and HFLAGS_BE flag, which would cause the immediate debug interrupt to be generated, e.g.: when DBCR0.ICMP bit is set by guest software and MSR.DE is not set. [1] https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf Signed-off-by: Bin Meng --- Changes in v2: - update commit message to use E500CORERM instead of PowerISA 2.07 target/ppc/helper_regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 9a691d6833..77bc57415c 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -63,10 +63,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (ppc_flags & POWERPC_FLAG_DE) { target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { + if ((dbcr0 & DBCR0_ICMP) && msr_de) { hflags |= 1 << HFLAGS_SE; } - if (dbcr0 & DBCR0_BRT) { + if ((dbcr0 & DBCR0_BRT) && msr_de) { hflags |= 1 << HFLAGS_BE; } } else { -- 2.25.1