From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Niklas Cassel <niklas.cassel@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
Date: Thu, 21 Apr 2022 16:36:19 +1000 [thread overview]
Message-ID: <20220421063630.1033608-21-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com>
From: Niklas Cassel <niklas.cassel@wdc.com>
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
option is disabled using rv32,mmu=off or rv64,mmu=off.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220414155510.1364147-1-niklas.cassel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 09609c96e8..b49c5361bd 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -230,8 +230,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(mc->fdt, cpu_name);
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
- (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_MMU)) {
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+ } else {
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ "riscv,none");
+ }
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.35.1
next prev parent reply other threads:[~2022-04-21 6:52 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 6:35 [PULL 00/31] riscv-to-apply queue Alistair Francis
2022-04-21 6:36 ` [PULL 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-04-21 6:36 ` [PULL 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-21 6:36 ` [PULL 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-21 6:36 ` [PULL 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-21 6:36 ` [PULL 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-21 6:36 ` [PULL 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-21 6:36 ` [PULL 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-21 6:36 ` [PULL 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-21 6:36 ` [PULL 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-21 6:36 ` [PULL 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-21 6:36 ` [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-21 6:36 ` [PULL 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-21 6:36 ` [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-21 6:36 ` [PULL 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-21 6:36 ` [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-21 6:36 ` [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-21 6:36 ` [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-21 6:36 ` [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-21 6:36 ` [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-21 6:36 ` Alistair Francis [this message]
2022-04-21 6:36 ` [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-21 6:36 ` [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-21 6:36 ` [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-21 6:36 ` [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-21 6:36 ` [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-21 6:36 ` [PULL 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-21 6:36 ` [PULL 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-21 6:36 ` [PULL 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-21 6:36 ` [PULL 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-21 6:36 ` [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-21 6:36 ` [PULL 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-21 15:03 ` [PULL 00/31] riscv-to-apply queue Richard Henderson
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