From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 28/31] target/riscv: machine: Add debug state description
Date: Thu, 21 Apr 2022 16:36:27 +1000 [thread overview]
Message-ID: <20220421063630.1033608-29-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com>
From: Bin Meng <bin.meng@windriver.com>
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 243f567949..2a437b29a1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool debug_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+ .name = "cpu/debug/type2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+ VMSTATE_UINTTL(maddress, type2_trigger_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+ .name = "cpu/debug",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = debug_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_rv128,
&vmstate_kvmtimer,
&vmstate_envcfg,
+ &vmstate_debug,
NULL
}
};
--
2.35.1
next prev parent reply other threads:[~2022-04-21 7:14 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 6:35 [PULL 00/31] riscv-to-apply queue Alistair Francis
2022-04-21 6:36 ` [PULL 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-04-21 6:36 ` [PULL 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-21 6:36 ` [PULL 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-21 6:36 ` [PULL 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-21 6:36 ` [PULL 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-21 6:36 ` [PULL 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-21 6:36 ` [PULL 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-21 6:36 ` [PULL 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-21 6:36 ` [PULL 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-21 6:36 ` [PULL 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-21 6:36 ` [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-21 6:36 ` [PULL 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-21 6:36 ` [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-21 6:36 ` [PULL 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-21 6:36 ` [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-21 6:36 ` [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-21 6:36 ` [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-21 6:36 ` [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-21 6:36 ` [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-21 6:36 ` [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-21 6:36 ` [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-21 6:36 ` [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-21 6:36 ` [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-21 6:36 ` [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-21 6:36 ` [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-21 6:36 ` [PULL 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-21 6:36 ` [PULL 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-21 6:36 ` Alistair Francis [this message]
2022-04-21 6:36 ` [PULL 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-21 6:36 ` [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-21 6:36 ` [PULL 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-21 15:03 ` [PULL 00/31] riscv-to-apply queue Richard Henderson
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