From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 02/31] riscv: opentitan: Connect opentitan SPI Host
Date: Thu, 21 Apr 2022 16:36:01 +1000 [thread overview]
Message-ID: <20220421063630.1033608-3-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com>
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 30 +++++++++++++++++++++---------
hw/riscv/opentitan.c | 36 ++++++++++++++++++++++++++++++++----
2 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 00da9ded43..68892cd8e5 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -23,11 +23,18 @@
#include "hw/intc/sifive_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
+#include "hw/ssi/ibex_spi_host.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
+enum {
+ OPENTITAN_SPI_HOST0,
+ OPENTITAN_SPI_HOST1,
+ OPENTITAN_NUM_SPI_HOSTS,
+};
+
struct LowRISCIbexSoCState {
/*< private >*/
SysBusDevice parent_obj;
@@ -37,6 +44,7 @@ struct LowRISCIbexSoCState {
SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
+ IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
MemoryRegion flash_mem;
MemoryRegion rom;
@@ -89,15 +97,19 @@ enum {
};
enum {
- IBEX_TIMER_TIMEREXPIRED0_0 = 126,
- IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
- IBEX_UART0_RX_TIMEOUT_IRQ = 7,
- IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
- IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
- IBEX_UART0_RX_OVERFLOW_IRQ = 4,
- IBEX_UART0_TX_EMPTY_IRQ = 3,
- IBEX_UART0_RX_WATERMARK_IRQ = 2,
- IBEX_UART0_TX_WATERMARK_IRQ = 1,
+ IBEX_UART0_TX_WATERMARK_IRQ = 1,
+ IBEX_UART0_RX_WATERMARK_IRQ = 2,
+ IBEX_UART0_TX_EMPTY_IRQ = 3,
+ IBEX_UART0_RX_OVERFLOW_IRQ = 4,
+ IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+ IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+ IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+ IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+ IBEX_TIMER_TIMEREXPIRED0_0 = 126,
+ IBEX_SPI_HOST0_ERR_IRQ = 150,
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
+ IBEX_SPI_HOST1_ERR_IRQ = 152,
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
};
#endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 833624d66c..2d401dcb23 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -120,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
+
+ for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
+ object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
+ TYPE_IBEX_SPI_HOST);
+ }
}
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
const MemMapEntry *memmap = ibex_memmap;
+ DeviceState *dev;
+ SysBusDevice *busdev;
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
@@ -209,14 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
IRQ_M_TIMER));
+ /* SPI-Hosts */
+ for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
+ dev = DEVICE(&(s->spi_host[i]));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
+
+ switch (i) {
+ case OPENTITAN_SPI_HOST0:
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_SPI_HOST0_ERR_IRQ));
+ sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ));
+ break;
+ case OPENTITAN_SPI_HOST1:
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_SPI_HOST1_ERR_IRQ));
+ sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ));
+ break;
+ }
+ }
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
- create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
- memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
- create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
- memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
--
2.35.1
next prev parent reply other threads:[~2022-04-21 6:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 6:35 [PULL 00/31] riscv-to-apply queue Alistair Francis
2022-04-21 6:36 ` [PULL 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-04-21 6:36 ` Alistair Francis [this message]
2022-04-21 6:36 ` [PULL 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-21 6:36 ` [PULL 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-21 6:36 ` [PULL 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-21 6:36 ` [PULL 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-21 6:36 ` [PULL 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-21 6:36 ` [PULL 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-21 6:36 ` [PULL 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-21 6:36 ` [PULL 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-21 6:36 ` [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-21 6:36 ` [PULL 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-21 6:36 ` [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-21 6:36 ` [PULL 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-21 6:36 ` [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-21 6:36 ` [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-21 6:36 ` [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-21 6:36 ` [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-21 6:36 ` [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-21 6:36 ` [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-21 6:36 ` [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-21 6:36 ` [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-21 6:36 ` [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-21 6:36 ` [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-21 6:36 ` [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-21 6:36 ` [PULL 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-21 6:36 ` [PULL 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-21 6:36 ` [PULL 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-21 6:36 ` [PULL 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-21 6:36 ` [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-21 6:36 ` [PULL 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-21 15:03 ` [PULL 00/31] riscv-to-apply queue Richard Henderson
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