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envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Atish Patra Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. This commit enforces the privilege version for csrs introduced in v1.12 or after. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 5 +++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..c3fd018ecb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 #if defined(TARGET_RISCV64) @@ -503,7 +503,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version =3D PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version =3D PRIV_VERSION_1_10_0; @@ -518,7 +520,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 84a398b205..8b6a1b90f1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2975,6 +2975,7 @@ static inline RISCVException riscv_csrrw_check(CPUR= ISCVState *env, { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fail= s */ int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; + int csr_min_priv =3D csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) int effective_priv =3D env->priv; =20 @@ -3007,6 +3008,10 @@ static inline RISCVException riscv_csrrw_check(CPU= RISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } =20 + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); } =20 --=20 2.35.1