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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 0/7] target/rx patch queue Date: Thu, 21 Apr 2022 10:31:07 -0700 Message-Id: <20220421173114.48357-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 401d46789410e88e9e90d76a11f46e8e9f358d55: Merge tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-21 08:04:43 -0700) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-rx-20220421 for you to fetch changes up to 724eaecec6d22cf3842f896684bdc5b79492f093: target/rx: update PC correctly in wait instruction (2022-04-21 10:09:12 -0700) ---------------------------------------------------------------- Fix usp/isp swapping upon clrpsw/setpsw. Fix psw.i/pc upon wait. Align dtb in ram. ---------------------------------------------------------------- Richard Henderson (4): target/rx: Put tb_flags into DisasContext target/rx: Store PSW.U in tb->flags target/rx: Move DISAS_UPDATE check for write to PSW target/rx: Swap stack pointers on clrpsw/setpsw instruction Tomoaki Kawada (2): target/rx: set PSW.I when executing wait instruction target/rx: update PC correctly in wait instruction Yoshinori Sato (1): hw/rx: rx-gdbsim DTB load address aligned of 16byte. target/rx/cpu.h | 1 + hw/rx/rx-gdbsim.c | 2 +- target/rx/op_helper.c | 1 + target/rx/translate.c | 69 +++++++++++++++++++++++++++------------------------ 4 files changed, 40 insertions(+), 33 deletions(-)