From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Tomoaki Kawada <i@yvt.jp>, Yoshinori Sato <ysato@users.sourceforge.jp>
Subject: [PULL 7/7] target/rx: update PC correctly in wait instruction
Date: Thu, 21 Apr 2022 10:31:14 -0700 [thread overview]
Message-ID: <20220421173114.48357-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org>
From: Tomoaki Kawada <i@yvt.jp>
`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.
This change fixes the wait instruction skipping the subsequent branch
when used in an idle loop like this:
0: wait
bra.b 0b
brk // should be unreachable
Signed-off-by: Tomoaki Kawada <i@yvt.jp>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220417060224.2131788-1-i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 63c062993e..62aee66937 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2285,7 +2285,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
{
if (is_privileged(ctx, 1)) {
- tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
+ tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_wait(cpu_env);
}
return true;
--
2.34.1
next prev parent reply other threads:[~2022-04-21 18:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-21 17:31 [PULL 0/7] target/rx patch queue Richard Henderson
2022-04-21 17:31 ` [PULL 1/7] target/rx: Put tb_flags into DisasContext Richard Henderson
2022-04-21 17:31 ` [PULL 2/7] target/rx: Store PSW.U in tb->flags Richard Henderson
2022-04-21 17:31 ` [PULL 3/7] target/rx: Move DISAS_UPDATE check for write to PSW Richard Henderson
2022-04-21 17:31 ` [PULL 4/7] target/rx: Swap stack pointers on clrpsw/setpsw instruction Richard Henderson
2022-04-21 17:31 ` [PULL 5/7] hw/rx: rx-gdbsim DTB load address aligned of 16byte Richard Henderson
2022-04-21 17:31 ` [PULL 6/7] target/rx: set PSW.I when executing wait instruction Richard Henderson
2022-04-21 17:31 ` Richard Henderson [this message]
2022-04-22 1:47 ` [PULL 0/7] target/rx patch queue Richard Henderson
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