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From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers
Date: Thu, 21 Apr 2022 14:39:15 -0700	[thread overview]
Message-ID: <20220421213917.368830-5-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20220421213917.368830-1-jcmvbkbc@gmail.com>

Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/translate.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 82a0dbf46d7c..c4991735ead7 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2615,15 +2615,13 @@ static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     uint32_t id = par[0] - CCOMPARE;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->nccompare);
     if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
         gen_io_start();
     }
     tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
-    gen_helper_update_ccompare(cpu_env, tmp);
-    tcg_temp_free(tmp);
+    gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id));
 #endif
 }
 
@@ -2643,11 +2641,9 @@ static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - DBREAKA;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->ndbreak);
-    gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
@@ -2656,11 +2652,9 @@ static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - DBREAKC;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->ndbreak);
-    gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
@@ -2669,11 +2663,9 @@ static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
 {
 #ifndef CONFIG_USER_ONLY
     unsigned id = par[0] - IBREAKA;
-    TCGv_i32 tmp = tcg_const_i32(id);
 
     assert(id < dc->config->nibreak);
-    gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
-    tcg_temp_free(tmp);
+    gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in);
 #endif
 }
 
-- 
2.30.2



  parent reply	other threads:[~2022-04-21 21:44 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21 21:39 [PATCH 0/6] target/xtensa: use tcg_constant_* where possible Max Filippov
2022-04-21 21:39 ` [PATCH 1/6] target/xtensa: use tcg_contatnt_* for numeric literals Max Filippov
2022-04-21 21:54   ` Richard Henderson
2022-04-21 21:39 ` [PATCH 2/6] target/xtensa: use tcg_constant_* for exceptions Max Filippov
2022-04-21 21:54   ` Richard Henderson
2022-04-21 21:39 ` [PATCH 3/6] target/xtensa: use tcg_constant_* for TLB opcodes Max Filippov
2022-04-21 21:55   ` Richard Henderson
2022-04-21 21:39 ` Max Filippov [this message]
2022-04-21 21:55   ` [PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers Richard Henderson
2022-04-21 21:39 ` [PATCH 5/6] target/xtensa: use tcg_constant_* for FPU conversion opcodes Max Filippov
2022-04-21 21:56   ` Richard Henderson
2022-04-21 21:39 ` [PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes Max Filippov
2022-04-21 21:57   ` Richard Henderson

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