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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/61] hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
Date: Fri, 22 Apr 2022 11:03:53 +0100	[thread overview]
Message-ID: <20220422100432.2288247-23-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220422100432.2288247-1-peter.maydell@linaro.org>

The GICv4 extends the redistributor register map -- where GICv3
had two 64KB frames per CPU, GICv4 has four frames. Add support
for the extra frame by using a new gicv3_redist_size() function
in the places in the GIC implementation which currently use
a fixed constant size for the redistributor register block.
(Until we implement the extra registers they will RAZ/WI.)

Any board that wants to use a GICv4 will need to also adjust
to handle the different sized redistributor register block;
that will be done separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-23-peter.maydell@linaro.org
---
 hw/intc/gicv3_internal.h           | 21 +++++++++++++++++++++
 include/hw/intc/arm_gicv3_common.h |  5 +++++
 hw/intc/arm_gicv3_common.c         |  2 +-
 hw/intc/arm_gicv3_redist.c         |  8 ++++----
 4 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 8d58d38836f..9720ccf7507 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -489,6 +489,27 @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH)
 
 /* Functions internal to the emulated GICv3 */
 
+/**
+ * gicv3_redist_size:
+ * @s: GICv3State
+ *
+ * Return the size of the redistributor register frame in bytes
+ * (which depends on what GIC version this is)
+ */
+static inline int gicv3_redist_size(GICv3State *s)
+{
+    /*
+     * Redistributor size is controlled by the redistributor GICR_TYPER.VLPIS.
+     * It's the same for every redistributor in the GIC, so arbitrarily
+     * use the register field in the first one.
+     */
+    if (s->cpu[0].gicr_typer & GICR_TYPER_VLPIS) {
+        return GICV4_REDIST_SIZE;
+    } else {
+        return GICV3_REDIST_SIZE;
+    }
+}
+
 /**
  * gicv3_intid_is_special:
  * @intid: interrupt ID
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 08b27789385..40bc404a652 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -38,7 +38,12 @@
 
 #define GICV3_LPI_INTID_START 8192
 
+/*
+ * The redistributor in GICv3 has two 64KB frames per CPU; in
+ * GICv4 it has four 64KB frames per CPU.
+ */
 #define GICV3_REDIST_SIZE 0x20000
+#define GICV4_REDIST_SIZE 0x40000
 
 /* Number of SGI target-list bits */
 #define GICV3_TARGETLIST_BITS 16
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index dcc5ce28c6a..18999e3c8bb 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -295,7 +295,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 
         memory_region_init_io(&region->iomem, OBJECT(s),
                               ops ? &ops[1] : NULL, region, name,
-                              s->redist_region_count[i] * GICV3_REDIST_SIZE);
+                              s->redist_region_count[i] * gicv3_redist_size(s));
         sysbus_init_mmio(sbd, &region->iomem);
         g_free(name);
     }
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 7c75dd6f072..9f1fe09a78e 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -442,8 +442,8 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
      * in the memory map); if so then the GIC has multiple MemoryRegions
      * for the redistributors.
      */
-    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
-    offset %= GICV3_REDIST_SIZE;
+    cpuidx = region->cpuidx + offset / gicv3_redist_size(s);
+    offset %= gicv3_redist_size(s);
 
     cs = &s->cpu[cpuidx];
 
@@ -501,8 +501,8 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
      * in the memory map); if so then the GIC has multiple MemoryRegions
      * for the redistributors.
      */
-    cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
-    offset %= GICV3_REDIST_SIZE;
+    cpuidx = region->cpuidx + offset / gicv3_redist_size(s);
+    offset %= gicv3_redist_size(s);
 
     cs = &s->cpu[cpuidx];
 
-- 
2.25.1



  parent reply	other threads:[~2022-04-22 10:56 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 10:03 [PULL 00/61] target-arm queue Peter Maydell
2022-04-22 10:03 ` [PULL 01/61] hw/intc/arm_gicv3_its: Add missing blank line Peter Maydell
2022-04-22 10:03 ` [PULL 02/61] hw/intc/arm_gicv3: Sanity-check num-cpu property Peter Maydell
2022-04-22 10:03 ` [PULL 03/61] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count Peter Maydell
2022-04-22 10:03 ` [PULL 04/61] hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers Peter Maydell
2022-04-22 10:03 ` [PULL 05/61] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 Peter Maydell
2022-04-22 10:03 ` [PULL 06/61] hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" Peter Maydell
2022-04-22 10:03 ` [PULL 07/61] hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 Peter Maydell
2022-04-22 10:03 ` [PULL 08/61] hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI Peter Maydell
2022-04-22 10:03 ` [PULL 09/61] hw/intc/arm_gicv3_its: Implement VMAPP Peter Maydell
2022-04-22 10:03 ` [PULL 10/61] hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE Peter Maydell
2022-04-22 10:03 ` [PULL 11/61] hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" Peter Maydell
2022-04-22 10:03 ` [PULL 12/61] hw/intc/arm_gicv3_its: Factor out CTE lookup sequence Peter Maydell
2022-04-22 10:03 ` [PULL 13/61] hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code Peter Maydell
2022-04-22 10:03 ` [PULL 14/61] hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() Peter Maydell
2022-04-22 10:03 ` [PULL 15/61] hw/intc/arm_gicv3: Keep pointers to every connected ITS Peter Maydell
2022-04-22 10:03 ` [PULL 16/61] hw/intc/arm_gicv3_its: Implement VMOVP Peter Maydell
2022-04-22 10:03 ` [PULL 17/61] hw/intc/arm_gicv3_its: Implement VSYNC Peter Maydell
2022-04-22 10:03 ` [PULL 18/61] hw/intc/arm_gicv3_its: Implement INV command properly Peter Maydell
2022-04-22 10:03 ` [PULL 19/61] hw/intc/arm_gicv3_its: Implement INV for virtual interrupts Peter Maydell
2022-04-22 10:03 ` [PULL 20/61] hw/intc/arm_gicv3_its: Implement VMOVI Peter Maydell
2022-04-22 10:03 ` [PULL 21/61] hw/intc/arm_gicv3_its: Implement VINVALL Peter Maydell
2022-04-22 10:03 ` Peter Maydell [this message]
2022-04-22 10:03 ` [PULL 23/61] hw/intc/arm_gicv3: Implement new GICv4 redistributor registers Peter Maydell
2022-04-22 10:03 ` [PULL 24/61] hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() Peter Maydell
2022-04-22 10:03 ` [PULL 25/61] hw/intc/arm_gicv3_cpuif: Support vLPIs Peter Maydell
2022-04-22 10:03 ` [PULL 26/61] hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Peter Maydell
2022-04-22 10:03 ` [PULL 27/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic Peter Maydell
2022-04-22 10:03 ` [PULL 28/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic Peter Maydell
2022-04-22 10:04 ` [PULL 29/61] hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes Peter Maydell
2022-04-22 10:04 ` [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code Peter Maydell
2022-04-22 10:04 ` [PULL 31/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 32/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() Peter Maydell
2022-04-22 10:04 ` [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling Peter Maydell
2022-04-22 10:04 ` [PULL 34/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 35/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() Peter Maydell
2022-04-22 10:04 ` [PULL 36/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4 Peter Maydell
2022-04-22 10:04 ` [PULL 38/61] hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 Peter Maydell
2022-04-22 10:04 ` [PULL 39/61] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() Peter Maydell
2022-04-22 10:04 ` [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity Peter Maydell
2022-04-22 10:04 ` [PULL 41/61] hw/arm/virt: Support TCG GICv4 Peter Maydell
2022-04-22 10:04 ` [PULL 42/61] target/arm: Update ISAR fields for ARMv8.8 Peter Maydell
2022-04-22 10:04 ` [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8 Peter Maydell
2022-04-22 10:04 ` [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2 Peter Maydell
2022-04-22 10:04 ` [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool Peter Maydell
2022-04-22 10:04 ` [PULL 46/61] target/arm: Change CPUArchState.aarch64 " Peter Maydell
2022-04-22 10:04 ` [PULL 47/61] target/arm: Extend store_cpu_offset to take field size Peter Maydell
2022-04-22 10:04 ` [PULL 48/61] target/arm: Change DisasContext.thumb to bool Peter Maydell
2022-04-22 10:04 ` [PULL 49/61] target/arm: Change CPUArchState.thumb " Peter Maydell
2022-04-22 10:04 ` [PULL 50/61] target/arm: Remove fpexc32_access Peter Maydell
2022-04-22 10:04 ` [PULL 51/61] target/arm: Split out set_btype_raw Peter Maydell
2022-04-22 10:04 ` [PULL 52/61] target/arm: Split out gen_rebuild_hflags Peter Maydell
2022-04-22 10:04 ` [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c Peter Maydell
2022-04-22 10:04 ` [PULL 54/61] target/arm: Simplify gen_sar Peter Maydell
2022-04-22 10:04 ` [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI Peter Maydell
2022-04-22 10:04 ` [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c Peter Maydell
2022-04-22 10:04 ` [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c Peter Maydell
2022-04-22 10:04 ` [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32 Peter Maydell
2022-04-22 10:04 ` [PULL 59/61] target/arm: Use tcg_constant in translate-vfp.c Peter Maydell
2022-04-22 10:04 ` [PULL 60/61] target/arm: Use tcg_constant_i32 in translate.h Peter Maydell
2022-04-22 10:04 ` [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() Peter Maydell
2022-04-22 11:41 ` [PULL 00/61] target-arm queue Richard Henderson
2022-04-22 13:48   ` Peter Maydell

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