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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c
Date: Fri, 22 Apr 2022 11:04:28 +0100	[thread overview]
Message-ID: <20220422100432.2288247-58-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220422100432.2288247-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Use tcg_constant_{i32,i64} as appropriate throughout.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-neon.c | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 384604c0095..2e4d1ec87d9 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -447,7 +447,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
     int mmu_idx = get_mem_index(s);
     int size = a->size;
     TCGv_i64 tmp64;
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -513,7 +513,6 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
 
     tmp64 = tcg_temp_new_i64();
     addr = tcg_temp_new_i32();
-    tmp = tcg_const_i32(1 << size);
     load_reg_var(s, addr, a->rn);
 
     mop = endian | size | align;
@@ -530,7 +529,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
                     neon_load_element64(tmp64, tt, n, size);
                     gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop);
                 }
-                tcg_gen_add_i32(addr, addr, tmp);
+                tcg_gen_addi_i32(addr, addr, 1 << size);
 
                 /* Subsequent memory operations inherit alignment */
                 mop &= ~MO_AMASK;
@@ -538,7 +537,6 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
         }
     }
     tcg_temp_free_i32(addr);
-    tcg_temp_free_i32(tmp);
     tcg_temp_free_i64(tmp64);
 
     gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
@@ -1348,7 +1346,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
      * To avoid excessive duplication of ops we implement shift
      * by immediate using the variable shift operations.
      */
-    constimm = tcg_const_i64(dup_const(a->size, a->shift));
+    constimm = tcg_constant_i64(dup_const(a->size, a->shift));
 
     for (pass = 0; pass < a->q + 1; pass++) {
         TCGv_i64 tmp = tcg_temp_new_i64();
@@ -1358,7 +1356,6 @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
         write_neon_element64(tmp, a->vd, pass, MO_64);
         tcg_temp_free_i64(tmp);
     }
-    tcg_temp_free_i64(constimm);
     return true;
 }
 
@@ -1394,7 +1391,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
      * To avoid excessive duplication of ops we implement shift
      * by immediate using the variable shift operations.
      */
-    constimm = tcg_const_i32(dup_const(a->size, a->shift));
+    constimm = tcg_constant_i32(dup_const(a->size, a->shift));
     tmp = tcg_temp_new_i32();
 
     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
@@ -1403,7 +1400,6 @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
         write_neon_element32(tmp, a->vd, pass, MO_32);
     }
     tcg_temp_free_i32(tmp);
-    tcg_temp_free_i32(constimm);
     return true;
 }
 
@@ -1457,7 +1453,7 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
      * This is always a right shift, and the shiftfn is always a
      * left-shift helper, which thus needs the negated shift count.
      */
-    constimm = tcg_const_i64(-a->shift);
+    constimm = tcg_constant_i64(-a->shift);
     rm1 = tcg_temp_new_i64();
     rm2 = tcg_temp_new_i64();
     rd = tcg_temp_new_i32();
@@ -1477,7 +1473,6 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
     tcg_temp_free_i32(rd);
     tcg_temp_free_i64(rm1);
     tcg_temp_free_i64(rm2);
-    tcg_temp_free_i64(constimm);
 
     return true;
 }
@@ -1521,7 +1516,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
         /* size == 2 */
         imm = -a->shift;
     }
-    constimm = tcg_const_i32(imm);
+    constimm = tcg_constant_i32(imm);
 
     /* Load all inputs first to avoid potential overwrite */
     rm1 = tcg_temp_new_i32();
@@ -1546,7 +1541,6 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
 
     shiftfn(rm3, rm3, constimm);
     shiftfn(rm4, rm4, constimm);
-    tcg_temp_free_i32(constimm);
 
     tcg_gen_concat_i32_i64(rtmp, rm3, rm4);
     tcg_temp_free_i32(rm4);
@@ -2911,7 +2905,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
         return true;
     }
 
-    desc = tcg_const_i32((a->vn << 2) | a->len);
+    desc = tcg_constant_i32((a->vn << 2) | a->len);
     def = tcg_temp_new_i64();
     if (a->op) {
         read_neon_element64(def, a->vd, 0, MO_64);
@@ -2926,7 +2920,6 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
 
     tcg_temp_free_i64(def);
     tcg_temp_free_i64(val);
-    tcg_temp_free_i32(desc);
     return true;
 }
 
-- 
2.25.1



  parent reply	other threads:[~2022-04-22 11:40 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 10:03 [PULL 00/61] target-arm queue Peter Maydell
2022-04-22 10:03 ` [PULL 01/61] hw/intc/arm_gicv3_its: Add missing blank line Peter Maydell
2022-04-22 10:03 ` [PULL 02/61] hw/intc/arm_gicv3: Sanity-check num-cpu property Peter Maydell
2022-04-22 10:03 ` [PULL 03/61] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count Peter Maydell
2022-04-22 10:03 ` [PULL 04/61] hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers Peter Maydell
2022-04-22 10:03 ` [PULL 05/61] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 Peter Maydell
2022-04-22 10:03 ` [PULL 06/61] hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" Peter Maydell
2022-04-22 10:03 ` [PULL 07/61] hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 Peter Maydell
2022-04-22 10:03 ` [PULL 08/61] hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI Peter Maydell
2022-04-22 10:03 ` [PULL 09/61] hw/intc/arm_gicv3_its: Implement VMAPP Peter Maydell
2022-04-22 10:03 ` [PULL 10/61] hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE Peter Maydell
2022-04-22 10:03 ` [PULL 11/61] hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" Peter Maydell
2022-04-22 10:03 ` [PULL 12/61] hw/intc/arm_gicv3_its: Factor out CTE lookup sequence Peter Maydell
2022-04-22 10:03 ` [PULL 13/61] hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code Peter Maydell
2022-04-22 10:03 ` [PULL 14/61] hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() Peter Maydell
2022-04-22 10:03 ` [PULL 15/61] hw/intc/arm_gicv3: Keep pointers to every connected ITS Peter Maydell
2022-04-22 10:03 ` [PULL 16/61] hw/intc/arm_gicv3_its: Implement VMOVP Peter Maydell
2022-04-22 10:03 ` [PULL 17/61] hw/intc/arm_gicv3_its: Implement VSYNC Peter Maydell
2022-04-22 10:03 ` [PULL 18/61] hw/intc/arm_gicv3_its: Implement INV command properly Peter Maydell
2022-04-22 10:03 ` [PULL 19/61] hw/intc/arm_gicv3_its: Implement INV for virtual interrupts Peter Maydell
2022-04-22 10:03 ` [PULL 20/61] hw/intc/arm_gicv3_its: Implement VMOVI Peter Maydell
2022-04-22 10:03 ` [PULL 21/61] hw/intc/arm_gicv3_its: Implement VINVALL Peter Maydell
2022-04-22 10:03 ` [PULL 22/61] hw/intc/arm_gicv3: Implement GICv4's new redistributor frame Peter Maydell
2022-04-22 10:03 ` [PULL 23/61] hw/intc/arm_gicv3: Implement new GICv4 redistributor registers Peter Maydell
2022-04-22 10:03 ` [PULL 24/61] hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() Peter Maydell
2022-04-22 10:03 ` [PULL 25/61] hw/intc/arm_gicv3_cpuif: Support vLPIs Peter Maydell
2022-04-22 10:03 ` [PULL 26/61] hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily Peter Maydell
2022-04-22 10:03 ` [PULL 27/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic Peter Maydell
2022-04-22 10:03 ` [PULL 28/61] hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic Peter Maydell
2022-04-22 10:04 ` [PULL 29/61] hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes Peter Maydell
2022-04-22 10:04 ` [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code Peter Maydell
2022-04-22 10:04 ` [PULL 31/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 32/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() Peter Maydell
2022-04-22 10:04 ` [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling Peter Maydell
2022-04-22 10:04 ` [PULL 34/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 35/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() Peter Maydell
2022-04-22 10:04 ` [PULL 36/61] hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() Peter Maydell
2022-04-22 10:04 ` [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4 Peter Maydell
2022-04-22 10:04 ` [PULL 38/61] hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 Peter Maydell
2022-04-22 10:04 ` [PULL 39/61] hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() Peter Maydell
2022-04-22 10:04 ` [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity Peter Maydell
2022-04-22 10:04 ` [PULL 41/61] hw/arm/virt: Support TCG GICv4 Peter Maydell
2022-04-22 10:04 ` [PULL 42/61] target/arm: Update ISAR fields for ARMv8.8 Peter Maydell
2022-04-22 10:04 ` [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8 Peter Maydell
2022-04-22 10:04 ` [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2 Peter Maydell
2022-04-22 10:04 ` [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool Peter Maydell
2022-04-22 10:04 ` [PULL 46/61] target/arm: Change CPUArchState.aarch64 " Peter Maydell
2022-04-22 10:04 ` [PULL 47/61] target/arm: Extend store_cpu_offset to take field size Peter Maydell
2022-04-22 10:04 ` [PULL 48/61] target/arm: Change DisasContext.thumb to bool Peter Maydell
2022-04-22 10:04 ` [PULL 49/61] target/arm: Change CPUArchState.thumb " Peter Maydell
2022-04-22 10:04 ` [PULL 50/61] target/arm: Remove fpexc32_access Peter Maydell
2022-04-22 10:04 ` [PULL 51/61] target/arm: Split out set_btype_raw Peter Maydell
2022-04-22 10:04 ` [PULL 52/61] target/arm: Split out gen_rebuild_hflags Peter Maydell
2022-04-22 10:04 ` [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c Peter Maydell
2022-04-22 10:04 ` [PULL 54/61] target/arm: Simplify gen_sar Peter Maydell
2022-04-22 10:04 ` [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI Peter Maydell
2022-04-22 10:04 ` [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c Peter Maydell
2022-04-22 10:04 ` Peter Maydell [this message]
2022-04-22 10:04 ` [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32 Peter Maydell
2022-04-22 10:04 ` [PULL 59/61] target/arm: Use tcg_constant in translate-vfp.c Peter Maydell
2022-04-22 10:04 ` [PULL 60/61] target/arm: Use tcg_constant_i32 in translate.h Peter Maydell
2022-04-22 10:04 ` [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() Peter Maydell
2022-04-22 11:41 ` [PULL 00/61] target-arm queue Richard Henderson
2022-04-22 13:48   ` Peter Maydell

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