From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 3/7] tests/tcg/xtensa: fix watchpoint test
Date: Wed, 27 Apr 2022 10:21:36 -0700 [thread overview]
Message-ID: <20220427172140.1406059-4-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20220427172140.1406059-1-jcmvbkbc@gmail.com>
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't
hardcode register numbers in the test as 0 and 1, use macros that only
index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_break.S | 86 +++++++++++++++++++----------------
1 file changed, 46 insertions(+), 40 deletions(-)
diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S
index 3379a3f9f06e..3aa18b5cec3f 100644
--- a/tests/tcg/xtensa/test_break.S
+++ b/tests/tcg/xtensa/test_break.S
@@ -200,64 +200,70 @@ test_end
.endm
#if XCHAL_NUM_DBREAK
+#define DB0 0
+#if XCHAL_NUM_DBREAK > 1
+#define DB1 1
+#else
+#define DB1 0
+#endif
test dbreak_exact
- dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
- dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
- dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
+ dbreak_test DB0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
+ dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
+ dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
- dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
- dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
- dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
+ dbreak_test DB1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
+ dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
+ dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
test_end
-test dbreak_overlap
- dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
- dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
+test DBdbreak_overlap
+ dbreak_test DB0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
+ dbreak_test DB1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
- dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
- dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
+ dbreak_test DB0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
+ dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
- dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
- dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
+ dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
+ dbreak_test DB1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
- dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
- dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
- dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i
+ dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
+ dbreak_test DB1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
+ dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007c, l32i
- dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
- dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
- dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i
+ dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
+ dbreak_test DB0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
+ dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000078, l32i
- dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
- dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
- dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i
+ dbreak_test DB0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
+ dbreak_test DB1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
+ dbreak_test DB0, 0x40000020, 0xd0000060, 0xd0000074, l32i
- dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
- dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
+ dbreak_test DB0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
+ dbreak_test DB1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
- dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
- dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
+ dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
+ dbreak_test DB1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
- dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
- dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
+ dbreak_test DB0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
+ dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
- dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i
- dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i
- dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i
+ dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007b, s8i
+ dbreak_test DB1, 0x80000038, 0xd0000078, 0xd000007a, s16i
+ dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007c, s32i
- dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i
- dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i
- dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i
+ dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000075, s8i
+ dbreak_test DB0, 0x80000030, 0xd0000070, 0xd0000076, s16i
+ dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000078, s32i
- dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i
- dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i
- dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i
+ dbreak_test DB0, 0x80000020, 0xd0000060, 0xd000006f, s8i
+ dbreak_test DB1, 0x80000020, 0xd0000060, 0xd0000070, s16i
+ dbreak_test DB0, 0x80000020, 0xd0000060, 0xd0000074, s32i
test_end
-test dbreak_invalid
- dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
- dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
+test DBdbreak_invalid
+ dbreak_test DB0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
+ dbreak_test DB1, 0x40000035, 0xd0000072, 0xd0000070, l32i
test_end
#endif
--
2.30.2
next prev parent reply other threads:[~2022-04-27 17:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-27 17:21 [PATCH 0/7] tests/tcg/xtensa: test fixes and improvements Max Filippov
2022-04-27 17:21 ` [PATCH 1/7] tests/tcg/xtensa: fix build for cores without windowed registers Max Filippov
2022-04-27 17:21 ` [PATCH 2/7] tests/tcg/xtensa: restore vecbase SR after test Max Filippov
2022-04-27 17:21 ` Max Filippov [this message]
2022-04-27 17:21 ` [PATCH 4/7] tests/tcg/xtensa: remove dependency on the loop option Max Filippov
2022-04-27 17:21 ` [PATCH 5/7] tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Max Filippov
2022-04-27 17:21 ` [PATCH 6/7] tests/tcg/xtensa: enable mmu " Max Filippov
2022-04-27 17:21 ` [PATCH 7/7] tests/tcg/xtensa: fix vectors and checks in timer test Max Filippov
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