From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>, qemu-devel@nongnu.org
Subject: [RFC PATCH 3/4] tcg/ppc: Optimize memory ordering generation with lwsync
Date: Tue, 3 May 2022 20:33:33 +1000 [thread overview]
Message-ID: <20220503103334.2046414-3-npiggin@gmail.com> (raw)
In-Reply-To: <20220503103334.2046414-1-npiggin@gmail.com>
lwsync orders more than just LD_LD, importantly it matches x86 and
s390 default memory ordering.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 2 ++
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c2b6c987c0..0b0e9761cd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -28,6 +28,8 @@
#define TCG_GUEST_DEFAULT_MO 0
+#define PPC_LWSYNC_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
+
#define TARGET_PAGE_BITS_64K 16
#define TARGET_PAGE_BITS_16M 24
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 3ff845d063..b87fc2383e 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1834,7 +1834,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
{
uint32_t insn = HWSYNC;
a0 &= TCG_MO_ALL;
- if (a0 == TCG_MO_LD_LD) {
+ if ((a0 & PPC_LWSYNC_MO) == a0) {
insn = LWSYNC;
}
tcg_out32(s, insn);
--
2.35.1
next prev parent reply other threads:[~2022-05-03 10:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 10:33 [RFC PATCH 1/4] target/ppc: Fix eieio memory ordering semantics Nicholas Piggin
2022-05-03 10:33 ` [RFC PATCH 2/4] tcg/ppc: ST_ST memory ordering is not provided with eieio Nicholas Piggin
2022-05-03 15:01 ` Richard Henderson
2022-05-03 10:33 ` Nicholas Piggin [this message]
2022-05-03 14:53 ` [RFC PATCH 3/4] tcg/ppc: Optimize memory ordering generation with lwsync Richard Henderson
2022-05-03 10:33 ` [RFC PATCH 4/4] target/ppc: Implement lwsync with weaker memory ordering Nicholas Piggin
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