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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg
Date: Thu,  5 May 2022 10:11:27 +0100	[thread overview]
Message-ID: <20220505091147.2657652-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Rearrange the values of the enumerators of CPAccessResult
so that we may directly extract the target el. For the two
special cases in access_check_cp_reg, use CPAccessResult.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    | 26 ++++++++++++--------
 target/arm/op_helper.c | 56 +++++++++++++++++++++---------------------
 2 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 8064c0763e2..7f2c30eab1c 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -167,26 +167,32 @@ static inline bool cptype_valid(int cptype)
 typedef enum CPAccessResult {
     /* Access is permitted */
     CP_ACCESS_OK = 0,
+
+    /*
+     * Combined with one of the following, the low 2 bits indicate the
+     * target exception level.  If 0, the exception is taken to the usual
+     * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+     */
+    CP_ACCESS_EL_MASK = 3,
+
     /*
      * Access fails due to a configurable trap or enable which would
      * result in a categorized exception syndrome giving information about
      * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
-     * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
-     * PL1 if in EL0, otherwise to the current EL).
+     * 0xc or 0x18).
      */
-    CP_ACCESS_TRAP = 1,
+    CP_ACCESS_TRAP = (1 << 2),
+    CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
+    CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+
     /*
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
      */
-    CP_ACCESS_TRAP_UNCATEGORIZED = 2,
-    /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_EL2 = 3,
-    CP_ACCESS_TRAP_EL3 = 4,
-    /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
+    CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 67be91c7323..76499ffa149 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -632,11 +632,13 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
                                  uint32_t isread)
 {
     const ARMCPRegInfo *ri = rip;
+    CPAccessResult res = CP_ACCESS_OK;
     int target_el;
 
     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
-        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+        res = CP_ACCESS_TRAP;
+        goto fail;
     }
 
     /*
@@ -655,48 +657,46 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
         mask &= ~((1 << 4) | (1 << 14));
 
         if (env->cp15.hstr_el2 & mask) {
-            target_el = 2;
-            goto exept;
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
         }
     }
 
-    if (!ri->accessfn) {
+    if (ri->accessfn) {
+        res = ri->accessfn(env, ri, isread);
+    }
+    if (likely(res == CP_ACCESS_OK)) {
         return;
     }
 
-    switch (ri->accessfn(env, ri, isread)) {
-    case CP_ACCESS_OK:
-        return;
+ fail:
+    switch (res & ~CP_ACCESS_EL_MASK) {
     case CP_ACCESS_TRAP:
-        target_el = exception_target_el(env);
-        break;
-    case CP_ACCESS_TRAP_EL2:
-        /* Requesting a trap to EL2 when we're in EL3 is
-         * a bug in the access function.
-         */
-        assert(arm_current_el(env) != 3);
-        target_el = 2;
-        break;
-    case CP_ACCESS_TRAP_EL3:
-        target_el = 3;
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
-        target_el = exception_target_el(env);
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
-        target_el = 2;
-        syndrome = syn_uncategorized();
-        break;
-    case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
-        target_el = 3;
         syndrome = syn_uncategorized();
         break;
     default:
         g_assert_not_reached();
     }
 
-exept:
+    target_el = res & CP_ACCESS_EL_MASK;
+    switch (target_el) {
+    case 0:
+        target_el = exception_target_el(env);
+        break;
+    case 2:
+        assert(arm_current_el(env) != 3);
+        assert(arm_is_el2_enabled(env));
+        break;
+    case 3:
+        assert(arm_feature(env, ARM_FEATURE_EL3));
+        break;
+    default:
+        /* No "direct" traps to EL1 */
+        g_assert_not_reached();
+    }
+
     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 }
 
-- 
2.25.1



  parent reply	other threads:[~2022-05-05  9:58 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05  9:11 [PULL 00/23] target-arm queue Peter Maydell
2022-05-05  9:11 ` [PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user Peter Maydell
2022-05-05  9:11 ` [PULL 02/23] target/arm: Split out cpregs.h Peter Maydell
2022-05-05  9:11 ` Peter Maydell [this message]
2022-05-05  9:11 ` [PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Peter Maydell
2022-05-05  9:11 ` [PULL 05/23] target/arm: Make some more cpreg data static const Peter Maydell
2022-05-05  9:11 ` [PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits Peter Maydell
2022-05-05  9:11 ` [PULL 07/23] target/arm: Avoid bare abort() or assert(0) Peter Maydell
2022-05-05  9:11 ` [PULL 08/23] target/arm: Change cpreg access permissions to enum Peter Maydell
2022-05-05  9:11 ` [PULL 09/23] target/arm: Name CPState type Peter Maydell
2022-05-05  9:11 ` [PULL 10/23] target/arm: Name CPSecureState type Peter Maydell
2022-05-05  9:11 ` [PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases Peter Maydell
2022-05-05  9:11 ` [PULL 12/23] target/arm: Store cpregs key in the hash table directly Peter Maydell
2022-05-05  9:11 ` [PULL 13/23] target/arm: Merge allocation of the cpreg and its name Peter Maydell
2022-05-05  9:11 ` [PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable Peter Maydell
2022-05-05  9:11 ` [PULL 15/23] target/arm: Consolidate cpreg updates " Peter Maydell
2022-05-05  9:11 ` [PULL 16/23] target/arm: Use bool for is64 and ns " Peter Maydell
2022-05-05  9:11 ` [PULL 17/23] target/arm: Hoist isbanked computation " Peter Maydell
2022-05-05  9:11 ` [PULL 18/23] target/arm: Perform override check early " Peter Maydell
2022-05-05  9:11 ` [PULL 19/23] target/arm: Reformat comments " Peter Maydell
2022-05-05  9:11 ` [PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef " Peter Maydell
2022-05-05  9:11 ` [PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2 Peter Maydell
2022-05-05  9:11 ` [PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras Peter Maydell
2022-05-05  9:11 ` [PULL 23/23] target/arm: read access to performance counters from EL0 Peter Maydell
2022-05-05 17:56 ` [PULL 00/23] target-arm queue Richard Henderson

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