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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/5] gicv3: Use right number of prio bits for the CPU Date: Fri, 6 May 2022 17:21:24 +0100 Message-Id: <20220506162129.2896966-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset fills in an odd inconsistency in our GICv3 emulation that I noticed while I was doing the GICv4 work. At the moment we allow the CPU to specify the number of bits of virtual priority (via the ARMCPU::gic_vpribits field), but we always use 8 bits of physical priority, even though to my knowledge no real Arm CPU hardware has that many. This series makes the GICv3 emulation use a runtime-configurable number of physical priority bits, and sets it to match the number used by the various CPUs we implement (which is 5 for all the Cortex-Axx CPUs we emulate). Because changing the number of priority bits is a migration compatibility break, we use a compat property to keep the number of priority bits at 8 for older versions of the virt board. There is one TODO left in this series, which is that I don't know the right value to use for the A64FX, so I've guessed that it is 5, like all the Arm implementations. Patch 1 is an independent bugfix; patch 5 is cleanup. thanks -- PMM Peter Maydell (5): hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant hw/intc/arm_gicv3: Support configurable number of physical priority bits hw/intc/arm_gicv3: Use correct number of priority bits for the CPU hw/intc/arm_gicv3: Provide ich_num_aprs() include/hw/intc/arm_gicv3_common.h | 8 +- target/arm/cpu.h | 1 + hw/core/machine.c | 4 +- hw/intc/arm_gicv3_common.c | 5 + hw/intc/arm_gicv3_cpuif.c | 208 ++++++++++++++++++++--------- hw/intc/arm_gicv3_kvm.c | 16 ++- target/arm/cpu64.c | 9 ++ 7 files changed, 179 insertions(+), 72 deletions(-) -- 2.25.1