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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id q20-20020a1ce914000000b003942a244f3dsm4639373wmc.22.2022.05.13.00.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 00:51:55 -0700 (PDT) Date: Fri, 13 May 2022 09:51:54 +0200 From: Igor Mammedov To: Peter Maydell Cc: eric.auger@redhat.com, qemu-devel@nongnu.org Subject: Re: [PATCH v5 10/10] test: tpm-tis: Add Sysbus TPM-TIS device test Message-ID: <20220513095154.7a015ff9@redhat.com> In-Reply-To: References: <20200305165149.618-1-eric.auger@redhat.com> <20200305165149.618-11-eric.auger@redhat.com> <52bdff5a-f33a-c76b-0e04-b20970e3ec1d@redhat.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 12 May 2022 17:05:41 +0100 Peter Maydell wrote: > On Thu, 12 May 2022 at 16:59, Eric Auger wrote: > > > > Hi Peter, > > > > On 5/12/22 15:08, Peter Maydell wrote: > > > On Thu, 5 Mar 2020 at 16:52, Eric Auger wrote: > > >> The tests themselves are the same as the ISA device ones. > > >> Only the main() changes as the "tpm-tis-device" device gets > > >> instantiated. Also the base address of the device is not > > >> 0xFED40000 anymore but matches the base address of the > > >> ARM virt platform bus. > > >> > > >> Signed-off-by: Eric Auger > > >> Reviewed-by: Stefan Berger > > > Hi Eric; the commit adding this test is from back in 2020, but I've > > > just noticed something a bit odd about it: > > > > > >> + args = g_strdup_printf( > > >> + "-machine virt,gic-version=max -accel tcg " > > >> + "-chardev socket,id=chr,path=%s " > > >> + "-tpmdev emulator,id=dev,chardev=chr " > > >> + "-device tpm-tis-device,tpmdev=dev", > > >> + test.addr->u.q_unix.path); > > > This 'virt' command line doesn't specify a CPU type, so it > > > will end up running with a Cortex-A15 (32-bit). Was > > > that intended? Also, it will get a GICv3, which is a > > > definitely odd combination with an A15, which was a GICv2 CPU... > > no it is not intended. I guess it should include "-cpu max" too > > as arm-cpu-features.c does? > > Seems like a reasonable thing to set, yes. > > > > I noticed this because I have some recent GICv3 patches which > > > end up asserting if the GICv3 and a non-GICv3 CPU are used together, > > > and this test case triggers them. Since the user can also cause > > > an assert with that kind of command line I'm going to rework them > > > (either to make the virt board fail cleanly or else to make the > > > GICv3 code do something plausible even if the real hardware CPU > > > nominally didn't have a GICv3). But maybe we should make this > > > test case not use a non-standard combination anyway? (The meson > > > conversion seems to have resulted in this test being run under > > > qemu-system-arm as well, incidentally, so I guess we would want > > > it to specify either 'a 64 bit CPU and GICv3' or 'a 32 bit > > > CPU and GICv2' accordingly. Or limit the test to aarch64...) > > limiting the test to aarch64 may be enough? > > Mmm, if running the test under 'qemu-system-arm' isn't giving > us interesting extra coverage we might as well save the CI cycles. agreed, we probably should limit all ARM tests in bios-tables-test to aarch64 'qemu-system-arm' doesn't give us anything extra on top of what aarch64 already does. > > -- PMM >