* [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
@ 2022-05-13 22:14 Atish Patra
2022-05-14 2:21 ` Frank Chang
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Atish Patra @ 2022-05-13 22:14 UTC (permalink / raw)
To: qemu-devel
Cc: Atish Patra, Alistair Francis, Anup Patel, qemu-riscv, dylan,
Bin Meng, Frank Chang, Jim Shu
timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.
Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
hw/intc/riscv_aclint.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 0412edc98257..e6bceceefdbc 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
continue;
}
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
- i, env->timecmp);
+ mtimer->hartid_base + i,
+ env->timecmp);
}
return;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
@ 2022-05-14 2:21 ` Frank Chang
2022-05-14 4:42 ` Anup Patel
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Frank Chang @ 2022-05-14 2:21 UTC (permalink / raw)
To: Atish Patra
Cc: qemu-devel@nongnu.org Developers, Alistair Francis, Anup Patel,
open list:RISC-V, dylan, Bin Meng, Jim Shu
[-- Attachment #1: Type: text/plain, Size: 1164 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Sat, May 14, 2022 at 6:15 AM Atish Patra <atishp@rivosinc.com> wrote:
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register
> writable")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index 0412edc98257..e6bceceefdbc 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque,
> hwaddr addr,
> continue;
> }
> riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
> - i, env->timecmp);
> + mtimer->hartid_base + i,
> + env->timecmp);
> }
> return;
> }
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 1765 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
2022-05-14 2:21 ` Frank Chang
@ 2022-05-14 4:42 ` Anup Patel
2022-05-16 22:41 ` Alistair Francis
2022-05-16 23:10 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Anup Patel @ 2022-05-14 4:42 UTC (permalink / raw)
To: Atish Patra
Cc: QEMU Developers, Alistair Francis, open list:RISC-V, dylan,
Bin Meng, Frank Chang, Jim Shu
On Sat, May 14, 2022 at 3:45 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index 0412edc98257..e6bceceefdbc 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
> continue;
> }
> riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
> - i, env->timecmp);
> + mtimer->hartid_base + i,
> + env->timecmp);
> }
> return;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
2022-05-14 2:21 ` Frank Chang
2022-05-14 4:42 ` Anup Patel
@ 2022-05-16 22:41 ` Alistair Francis
2022-05-16 23:10 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2022-05-16 22:41 UTC (permalink / raw)
To: Atish Patra
Cc: qemu-devel@nongnu.org Developers, Alistair Francis, Anup Patel,
open list:RISC-V, Dylan Reid, Bin Meng, Frank Chang, Jim Shu
On Sat, May 14, 2022 at 8:15 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index 0412edc98257..e6bceceefdbc 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
> continue;
> }
> riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
> - i, env->timecmp);
> + mtimer->hartid_base + i,
> + env->timecmp);
> }
> return;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/intc: Pass correct hartid while updating mtimecmp
2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
` (2 preceding siblings ...)
2022-05-16 22:41 ` Alistair Francis
@ 2022-05-16 23:10 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2022-05-16 23:10 UTC (permalink / raw)
To: Atish Patra
Cc: qemu-devel@nongnu.org Developers, Alistair Francis, Anup Patel,
open list:RISC-V, Dylan Reid, Bin Meng, Frank Chang, Jim Shu
On Sat, May 14, 2022 at 8:15 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index 0412edc98257..e6bceceefdbc 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
> continue;
> }
> riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
> - i, env->timecmp);
> + mtimer->hartid_base + i,
> + env->timecmp);
> }
> return;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2022-05-13 22:14 [PATCH] hw/intc: Pass correct hartid while updating mtimecmp Atish Patra
2022-05-14 2:21 ` Frank Chang
2022-05-14 4:42 ` Anup Patel
2022-05-16 22:41 ` Alistair Francis
2022-05-16 23:10 ` Alistair Francis
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