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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 0/2] target/riscv: Cleanup exposed CPU properties
Date: Tue, 17 May 2022 14:10:58 +1000	[thread overview]
Message-ID: <20220517041100.93045-1-alistair.francis@opensource.wdc.com> (raw)

From: Alistair Francis <alistair.francis@wdc.com>

The RISC-V CPUs have been incorrectly enabling features in the named vendor
CPUs that aren't enabled in hardware. This patchset changes this so that
named vendor CPUs are not runtime configurable.

I was torn for the best approach here. The other idea I had was to disable
features by default and instead enable them in CPUs. I ended up going
this approach as I felt it made more sense to not expose configuration
options for vendor CPUs, it just seems difficult to support now that we have
a large list of CPUs

Alistair Francis (2):
  target/riscv: Don't expose the CPU properties on names CPUs
  target/riscv: Run extension checks for all CPUs

 target/riscv/cpu.c | 217 ++++++++++++++++++++++++++-------------------
 1 file changed, 125 insertions(+), 92 deletions(-)

-- 
2.35.1



             reply	other threads:[~2022-05-17  4:12 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-17  4:10 Alistair Francis [this message]
2022-05-17  4:10 ` [PATCH 1/2] target/riscv: Don't expose the CPU properties on names CPUs Alistair Francis
2022-05-17  4:11 ` [PATCH 2/2] target/riscv: Run extension checks for all CPUs Alistair Francis
2022-05-17  5:02   ` Weiwei Li
2022-05-17  5:07     ` Alistair Francis

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