From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v2 4/7] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller
Date: Mon, 16 May 2022 22:48:47 -0700 [thread overview]
Message-ID: <20220517054850.177016-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org>
This function is used only once, and will need modification
for Streaming SVE mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 11 -----------
target/arm/helper.c | 30 +++++++++++-------------------
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 6ca0e95746..36ff843cef 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -189,17 +189,6 @@ void arm_translate_init(void);
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
-/**
- * aarch64_sve_zcr_get_valid_len:
- * @cpu: cpu context
- * @start_len: maximum len to consider
- *
- * Return the maximum supported sve vector length <= @start_len.
- * Note that both @start_len and the return value are in units
- * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
- */
-uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
-
enum arm_fprounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5fd64b742a..0308920357 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6218,40 +6218,32 @@ int sve_exception_el(CPUARMState *env, int el)
return 0;
}
-uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
-{
- uint32_t end_len;
-
- start_len = MIN(start_len, ARM_MAX_VQ - 1);
- end_len = start_len;
-
- if (!test_bit(start_len, cpu->sve_vq_map)) {
- end_len = find_last_bit(cpu->sve_vq_map, start_len);
- assert(end_len < start_len);
- }
- return end_len;
-}
-
/*
* Given that SVE is enabled, return the vector length for EL.
*/
uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
{
ARMCPU *cpu = env_archcpu(env);
- uint32_t zcr_len = cpu->sve_max_vq - 1;
+ uint32_t len = cpu->sve_max_vq - 1;
+ uint32_t end_len;
if (el <= 1 &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
+ len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
}
if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
+ len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
+ len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
}
- return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
+ end_len = len;
+ if (!test_bit(len, cpu->sve_vq_map)) {
+ end_len = find_last_bit(cpu->sve_vq_map, len);
+ assert(end_len < len);
+ }
+ return end_len;
}
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.34.1
next prev parent reply other threads:[~2022-05-17 5:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 5:48 [PATCH v2 0/7] target/arm: SME prep patches Richard Henderson
2022-05-17 5:48 ` [PATCH v2 1/7] target/arm: Enable FEAT_HCX for -cpu max Richard Henderson
2022-05-17 5:48 ` [PATCH v2 2/7] target/arm: Use FIELD definitions for CPACR, CPTR_ELx Richard Henderson
2022-05-17 5:48 ` [PATCH v2 3/7] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Richard Henderson
2022-05-19 10:40 ` Peter Maydell
2022-05-19 16:33 ` Richard Henderson
2022-05-17 5:48 ` Richard Henderson [this message]
2022-05-17 5:48 ` [PATCH v2 5/7] target/arm: Use uint32_t instead of bitmap for sve vq's Richard Henderson
2022-05-19 12:10 ` Peter Maydell
2022-05-17 5:48 ` [PATCH v2 6/7] target/arm: Remove fp checks from sve_exception_el Richard Henderson
2022-05-19 11:36 ` Peter Maydell
2022-05-19 15:01 ` Richard Henderson
2022-05-17 5:48 ` [PATCH v2 7/7] target/arm: Add el_is_in_host Richard Henderson
2022-05-19 11:39 ` Peter Maydell
2022-05-19 15:04 ` Richard Henderson
2022-05-19 12:11 ` [PATCH v2 0/7] target/arm: SME prep patches Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220517054850.177016-5-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).