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envelope-from=prvs=1363756b6=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Tsukasa OI We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis Message-Id: Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b960473f7d..00a068668f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,14 +630,27 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ex= t_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extensi= on"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx =3D true; } =20 - if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension= "); + return; + } } =20 if (cpu->cfg.ext_zk) { @@ -663,7 +676,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) cpu->cfg.ext_zksh =3D true; } =20 - /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |=3D RVI; } @@ -734,20 +746,9 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } set_vext_version(env, vext_version); } - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ex= t_f) { - error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."= ); - return; - } if (cpu->cfg.ext_j) { ext |=3D RVJ; } - if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_z= fh || - cpu->cfg.ext_zfhmin)) { - error_setg(errp, - "'Zfinx' cannot be supported together with 'F', 'D',= 'Zfh'," - " 'Zfhmin'"); - return; - } =20 set_misa(env, env->misa_mxl, ext); } --=20 2.35.3