From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Bernhard Beschow" <shentey@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors
Date: Wed, 25 May 2022 08:44:19 +1000 [thread overview]
Message-ID: <20220524224428.552334-15-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220524224428.552334-1-alistair.francis@opensource.wdc.com>
From: Bernhard Beschow <shentey@gmail.com>
The QOM API already provides accessors for uint32 values, so reuse them.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220301225220.239065-3-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 24 ++++--------------------
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a2495b5ae7..e4c814a3ea 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -713,36 +713,20 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
-static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
- const char *name, void *opaque,
- Error **errp)
-{
- visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
-static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
- const char *name, void *opaque,
- Error **errp)
-{
- visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
static void sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
s->start_in_flash = false;
s->msel = 0;
- object_property_add(obj, "msel", "uint32",
- sifive_u_machine_get_uint32_prop,
- sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+ object_property_add_uint32_ptr(obj, "msel", &s->msel,
+ OBJ_PROP_FLAG_READWRITE);
object_property_set_description(obj, "msel",
"Mode Select (MSEL[3:0]) pin state");
s->serial = OTP_SERIAL;
- object_property_add(obj, "serial", "uint32",
- sifive_u_machine_get_uint32_prop,
- sifive_u_machine_set_uint32_prop, NULL, &s->serial);
+ object_property_add_uint32_ptr(obj, "serial", &s->serial,
+ OBJ_PROP_FLAG_READWRITE);
object_property_set_description(obj, "serial", "Board serial number");
}
--
2.35.3
next prev parent reply other threads:[~2022-05-24 22:55 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 22:44 [PULL 00/23] riscv-to-apply queue Alistair Francis
2022-05-24 22:44 ` [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access Alistair Francis
2022-05-24 22:44 ` [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store Alistair Francis
2022-05-24 22:44 ` [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp Alistair Francis
2022-05-24 22:44 ` [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string Alistair Francis
2022-05-24 22:44 ` [PULL 05/23] target/riscv: Add short-isa-string option Alistair Francis
2022-05-24 22:44 ` [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike) Alistair Francis
2022-05-24 22:44 ` [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) Alistair Francis
2022-05-24 22:44 ` [PULL 08/23] target/riscv: Fix coding style on "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 09/23] target/riscv: Disable "G" by default Alistair Francis
2022-05-24 22:44 ` [PULL 10/23] target/riscv: Change "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 11/23] target/riscv: FP extension requirements Alistair Francis
2022-05-24 22:44 ` [PULL 12/23] target/riscv: Move/refactor ISA extension checks Alistair Francis
2022-05-24 22:44 ` [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters Alistair Francis
2022-05-24 22:44 ` Alistair Francis [this message]
2022-05-24 22:44 ` [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
2022-05-24 22:44 ` [PULL 16/23] target/riscv: Fix typo of mimpid cpu option Alistair Francis
2022-05-24 22:44 ` [PULL 17/23] target/riscv: Fix csr number based privilege checking Alistair Francis
2022-05-24 22:44 ` [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Alistair Francis
2022-05-24 22:44 ` [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Alistair Francis
2022-05-24 22:44 ` [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices Alistair Francis
2022-05-24 22:44 ` [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string Alistair Francis
2022-05-24 22:44 ` [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01 Alistair Francis
2022-05-24 22:44 ` [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage Alistair Francis
2022-05-25 3:18 ` [PULL 00/23] riscv-to-apply queue Richard Henderson
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