From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
Date: Wed, 25 May 2022 08:44:20 +1000 [thread overview]
Message-ID: <20220524224428.552334-16-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220524224428.552334-1-alistair.francis@opensource.wdc.com>
From: Weiwei Li <liweiwei@iscas.ac.cn>
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 00a068668f..87e1eddce6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -584,18 +584,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
uint32_t ext = 0;
/* Do some ISA extension error checking */
- if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
- error_setg(errp,
- "I and E extensions are incompatible");
- return;
- }
-
- if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
- error_setg(errp,
- "Either I or E extension must be set");
- return;
- }
-
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d &&
@@ -610,6 +598,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_ifencei = true;
}
+ if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+ error_setg(errp,
+ "I and E extensions are incompatible");
+ return;
+ }
+
+ if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ error_setg(errp,
+ "Either I or E extension must be set");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.35.3
next prev parent reply other threads:[~2022-05-24 22:58 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 22:44 [PULL 00/23] riscv-to-apply queue Alistair Francis
2022-05-24 22:44 ` [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access Alistair Francis
2022-05-24 22:44 ` [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store Alistair Francis
2022-05-24 22:44 ` [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp Alistair Francis
2022-05-24 22:44 ` [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string Alistair Francis
2022-05-24 22:44 ` [PULL 05/23] target/riscv: Add short-isa-string option Alistair Francis
2022-05-24 22:44 ` [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike) Alistair Francis
2022-05-24 22:44 ` [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) Alistair Francis
2022-05-24 22:44 ` [PULL 08/23] target/riscv: Fix coding style on "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 09/23] target/riscv: Disable "G" by default Alistair Francis
2022-05-24 22:44 ` [PULL 10/23] target/riscv: Change "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 11/23] target/riscv: FP extension requirements Alistair Francis
2022-05-24 22:44 ` [PULL 12/23] target/riscv: Move/refactor ISA extension checks Alistair Francis
2022-05-24 22:44 ` [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters Alistair Francis
2022-05-24 22:44 ` [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors Alistair Francis
2022-05-24 22:44 ` Alistair Francis [this message]
2022-05-24 22:44 ` [PULL 16/23] target/riscv: Fix typo of mimpid cpu option Alistair Francis
2022-05-24 22:44 ` [PULL 17/23] target/riscv: Fix csr number based privilege checking Alistair Francis
2022-05-24 22:44 ` [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Alistair Francis
2022-05-24 22:44 ` [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Alistair Francis
2022-05-24 22:44 ` [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices Alistair Francis
2022-05-24 22:44 ` [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string Alistair Francis
2022-05-24 22:44 ` [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01 Alistair Francis
2022-05-24 22:44 ` [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage Alistair Francis
2022-05-25 3:18 ` [PULL 00/23] riscv-to-apply queue Richard Henderson
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