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envelope-from=prvs=1363756b6=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel Currently, the [m|s]tval CSRs are set with trapping instruction encoding only for illegal instruction traps taken at the time of instruction decoding. In RISC-V world, a valid instructions might also trap as illegal or virtual instruction based to trapping bits in various CSRs (such as mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 +++++++- target/riscv/cpu.c | 2 ++ target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 17 +++++++++++++---- 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 44975e3e5a..f08c3e8813 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -30,6 +30,12 @@ =20 #define TCG_GUEST_DEFAULT_MO 0 =20 +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + */ +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TYPE_RISCV_CPU "riscv-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU @@ -140,7 +146,7 @@ struct CPUArchState { target_ulong frm; =20 target_ulong badaddr; - uint32_t bins; + target_ulong bins; =20 target_ulong guest_phys_fault_addr; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe8ceb4133..ce1c257eef 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -406,6 +406,7 @@ void restore_state_to_opc(CPURISCVState *env, Transla= tionBlock *tb, } else { env->pc =3D data[0]; } + env->bins =3D data[1]; } =20 static void riscv_cpu_reset(DeviceState *dev) @@ -445,6 +446,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; + env->bins =3D 0; env->two_stage_lookup =3D false; =20 /* Initialized default priorities of local interrupts. */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b16bfe0182..d99fac9d2d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1371,6 +1371,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) tval =3D env->badaddr; break; case RISCV_EXCP_ILLEGAL_INST: + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: tval =3D env->bins; break; default: diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0cd1d9ee94..55a4713af2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -107,6 +107,8 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; + /* TCG of the current insn_start */ + TCGOp *insn_start; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -236,9 +238,6 @@ static void generate_exception_mtval(DisasContext *ct= x, int excp) =20 static void gen_exception_illegal(DisasContext *ctx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } =20 @@ -1017,6 +1016,13 @@ static uint32_t opcode_at(DisasContextBase *dcbase= , target_ulong pc) /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" =20 +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) +{ + assert(ctx->insn_start !=3D NULL); + tcg_set_insn_start_param(ctx->insn_start, 1, opc); + ctx->insn_start =3D NULL; +} + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t o= pcode) { /* @@ -1033,6 +1039,7 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx, uint16_t opcode) =20 /* Check for compressed insn */ if (extract16(opcode, 0, 2) !=3D 3) { + decode_save_opc(ctx, opcode); if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { @@ -1047,6 +1054,7 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx, uint16_t opcode) opcode32 =3D deposit32(opcode32, 16, 16, translator_lduw(env, &ctx->base, ctx->base.pc_next + 2)); + decode_save_opc(ctx, opcode32); ctx->opcode =3D opcode32; ctx->pc_succ_insn =3D ctx->base.pc_next + 4; =20 @@ -1113,7 +1121,8 @@ static void riscv_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0); + ctx->insn_start =3D tcg_last_op(); } =20 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) --=20 2.35.3