From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <apatel@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices
Date: Wed, 25 May 2022 08:44:25 +1000 [thread overview]
Message-ID: <20220524224428.552334-21-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220524224428.552334-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <apatel@ventanamicro.com>
When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.
In case of multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.
Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
platform FDT entries")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 244d6408b5..293e9c95b7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -478,10 +478,12 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
- platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
- memmap[VIRT_PLATFORM_BUS].base,
- memmap[VIRT_PLATFORM_BUS].size,
- VIRT_PLATFORM_BUS_IRQ);
+ if (!socket) {
+ platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+ memmap[VIRT_PLATFORM_BUS].base,
+ memmap[VIRT_PLATFORM_BUS].size,
+ VIRT_PLATFORM_BUS_IRQ);
+ }
g_free(plic_name);
@@ -561,11 +563,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
}
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
- platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
- memmap[VIRT_PLATFORM_BUS].base,
- memmap[VIRT_PLATFORM_BUS].size,
- VIRT_PLATFORM_BUS_IRQ);
-
g_free(imsic_name);
/* S-level IMSIC node */
@@ -704,10 +701,12 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
- platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
- memmap[VIRT_PLATFORM_BUS].base,
- memmap[VIRT_PLATFORM_BUS].size,
- VIRT_PLATFORM_BUS_IRQ);
+ if (!socket) {
+ platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+ memmap[VIRT_PLATFORM_BUS].base,
+ memmap[VIRT_PLATFORM_BUS].size,
+ VIRT_PLATFORM_BUS_IRQ);
+ }
g_free(aplic_name);
--
2.35.3
next prev parent reply other threads:[~2022-05-24 23:06 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 22:44 [PULL 00/23] riscv-to-apply queue Alistair Francis
2022-05-24 22:44 ` [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access Alistair Francis
2022-05-24 22:44 ` [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store Alistair Francis
2022-05-24 22:44 ` [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp Alistair Francis
2022-05-24 22:44 ` [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string Alistair Francis
2022-05-24 22:44 ` [PULL 05/23] target/riscv: Add short-isa-string option Alistair Francis
2022-05-24 22:44 ` [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike) Alistair Francis
2022-05-24 22:44 ` [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) Alistair Francis
2022-05-24 22:44 ` [PULL 08/23] target/riscv: Fix coding style on "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 09/23] target/riscv: Disable "G" by default Alistair Francis
2022-05-24 22:44 ` [PULL 10/23] target/riscv: Change "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 11/23] target/riscv: FP extension requirements Alistair Francis
2022-05-24 22:44 ` [PULL 12/23] target/riscv: Move/refactor ISA extension checks Alistair Francis
2022-05-24 22:44 ` [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters Alistair Francis
2022-05-24 22:44 ` [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors Alistair Francis
2022-05-24 22:44 ` [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
2022-05-24 22:44 ` [PULL 16/23] target/riscv: Fix typo of mimpid cpu option Alistair Francis
2022-05-24 22:44 ` [PULL 17/23] target/riscv: Fix csr number based privilege checking Alistair Francis
2022-05-24 22:44 ` [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Alistair Francis
2022-05-24 22:44 ` [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Alistair Francis
2022-05-24 22:44 ` Alistair Francis [this message]
2022-05-24 22:44 ` [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string Alistair Francis
2022-05-24 22:44 ` [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01 Alistair Francis
2022-05-24 22:44 ` [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage Alistair Francis
2022-05-25 3:18 ` [PULL 00/23] riscv-to-apply queue Richard Henderson
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