From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Tsukasa OI <research_trasio@irq.a4lg.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
Date: Wed, 25 May 2022 08:44:12 +1000 [thread overview]
Message-ID: <20220524224428.552334-8-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220524224428.552334-1-alistair.francis@opensource.wdc.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines. It now just prints error message and
quits (without coredumps and aborts).
This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 2d401dcb23..4495a2c039 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index dcb87b6cfd..d65d2fd869 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index cc8c7637cb..a2495b5ae7 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -830,8 +830,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
- sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
--
2.35.3
next prev parent reply other threads:[~2022-05-24 22:58 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 22:44 [PULL 00/23] riscv-to-apply queue Alistair Francis
2022-05-24 22:44 ` [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access Alistair Francis
2022-05-24 22:44 ` [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store Alistair Francis
2022-05-24 22:44 ` [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp Alistair Francis
2022-05-24 22:44 ` [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string Alistair Francis
2022-05-24 22:44 ` [PULL 05/23] target/riscv: Add short-isa-string option Alistair Francis
2022-05-24 22:44 ` [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike) Alistair Francis
2022-05-24 22:44 ` Alistair Francis [this message]
2022-05-24 22:44 ` [PULL 08/23] target/riscv: Fix coding style on "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 09/23] target/riscv: Disable "G" by default Alistair Francis
2022-05-24 22:44 ` [PULL 10/23] target/riscv: Change "G" expansion Alistair Francis
2022-05-24 22:44 ` [PULL 11/23] target/riscv: FP extension requirements Alistair Francis
2022-05-24 22:44 ` [PULL 12/23] target/riscv: Move/refactor ISA extension checks Alistair Francis
2022-05-24 22:44 ` [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters Alistair Francis
2022-05-24 22:44 ` [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors Alistair Francis
2022-05-24 22:44 ` [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
2022-05-24 22:44 ` [PULL 16/23] target/riscv: Fix typo of mimpid cpu option Alistair Francis
2022-05-24 22:44 ` [PULL 17/23] target/riscv: Fix csr number based privilege checking Alistair Francis
2022-05-24 22:44 ` [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode Alistair Francis
2022-05-24 22:44 ` [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps Alistair Francis
2022-05-24 22:44 ` [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices Alistair Francis
2022-05-24 22:44 ` [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string Alistair Francis
2022-05-24 22:44 ` [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01 Alistair Francis
2022-05-24 22:44 ` [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage Alistair Francis
2022-05-25 3:18 ` [PULL 00/23] riscv-to-apply queue Richard Henderson
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