From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Andrew Jeffery" <andrew@aj.id.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <steven_lee@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<jamin_lin@aspeedtech.com>
Subject: [PATCH v2 4/4] hw/gpio: replace HWADDR_PRIx with PRIx64
Date: Wed, 25 May 2022 13:34:44 +0800 [thread overview]
Message-ID: <20220525053444.27228-5-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20220525053444.27228-1-jamin_lin@aspeedtech.com>
1. replace HWADDR_PRIx with PRIx64
2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/gpio/aspeed_gpio.c | 8 ++++----
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index c834bf19f5..a62a673857 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -561,7 +561,7 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
reg = &agc->reg_table[idx];
if (reg->set_idx >= agc->nr_gpio_sets) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
- HWADDR_PRIx"\n", __func__, offset);
+ PRIx64"\n", __func__, offset);
return 0;
}
@@ -611,7 +611,7 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
- HWADDR_PRIx"\n", __func__, offset);
+ PRIx64"\n", __func__, offset);
return 0;
}
@@ -787,7 +787,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
reg = &agc->reg_table[idx];
if (reg->set_idx >= agc->nr_gpio_sets) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
- HWADDR_PRIx"\n", __func__, offset);
+ PRIx64"\n", __func__, offset);
return;
}
@@ -872,7 +872,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
- HWADDR_PRIx"\n", __func__, offset);
+ PRIx64"\n", __func__, offset);
return;
}
aspeed_gpio_update(s, set, set->data_value);
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
index 41b36524d0..904eecf62c 100644
--- a/include/hw/gpio/aspeed_gpio.h
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -67,7 +67,7 @@ enum GPIORegIndexType {
typedef struct AspeedGPIOReg {
uint16_t set_idx;
enum GPIORegType type;
- } AspeedGPIOReg;
+} AspeedGPIOReg;
struct AspeedGPIOClass {
SysBusDevice parent_obj;
--
2.17.1
next prev parent reply other threads:[~2022-05-25 6:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 5:34 [PATCH v2 0/4] hw/gpio Add ASPEED GPIO model for AST1030 Jamin Lin
2022-05-25 5:34 ` [PATCH v2 1/4] hw/gpio Add GPIO read/write trace event Jamin Lin
2022-05-25 5:34 ` [PATCH v2 2/4] hw/gpio: Add ASPEED GPIO model for AST1030 Jamin Lin
2022-05-25 6:26 ` Cédric Le Goater
2022-05-25 5:34 ` [PATCH v2 3/4] hw/gpio support GPIO index mode for write operation Jamin Lin
2022-05-25 7:54 ` Cédric Le Goater
2022-05-25 5:34 ` Jamin Lin [this message]
2022-05-25 6:26 ` [PATCH v2 4/4] hw/gpio: replace HWADDR_PRIx with PRIx64 Cédric Le Goater
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