From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PULL 01/17] target/i386: Remove LBREn bit check when access Arch LBR MSRs
Date: Wed, 25 May 2022 21:28:36 +0200 [thread overview]
Message-ID: <20220525192852.301633-2-pbonzini@redhat.com> (raw)
In-Reply-To: <20220525192852.301633-1-pbonzini@redhat.com>
From: Yang Weijiang <weijiang.yang@intel.com>
Live migration can happen when Arch LBR LBREn bit is cleared,
e.g., when migration happens after guest entered SMM mode.
In this case, we still need to migrate Arch LBR MSRs.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220517155024.33270-1-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/kvm/kvm.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index a9ee8eebd7..e2d675115b 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -3373,15 +3373,14 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
int i, ret;
/*
- * Only migrate Arch LBR states when: 1) Arch LBR is enabled
- * for migrated vcpu. 2) the host Arch LBR depth equals that
- * of source guest's, this is to avoid mismatch of guest/host
- * config for the msr hence avoid unexpected misbehavior.
+ * Only migrate Arch LBR states when the host Arch LBR depth
+ * equals that of source guest's, this is to avoid mismatch
+ * of guest/host config for the msr hence avoid unexpected
+ * misbehavior.
*/
ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
- if (ret == 1 && (env->msr_lbr_ctl & 0x1) && !!depth &&
- depth == env->msr_lbr_depth) {
+ if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
@@ -3801,13 +3800,11 @@ static int kvm_get_msrs(X86CPU *cpu)
if (kvm_enabled() && cpu->enable_pmu &&
(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
- uint64_t ctl, depth;
- int i, ret2;
+ uint64_t depth;
+ int i, ret;
- ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_CTL, &ctl);
- ret2 = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
- if (ret == 1 && ret2 == 1 && (ctl & 0x1) &&
- depth == ARCH_LBR_NR_ENTRIES) {
+ ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
+ if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
--
2.36.1
next prev parent reply other threads:[~2022-05-25 19:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-25 19:28 [PULL 00/17] Misc patches for 2022-05-25 Paolo Bonzini
2022-05-25 19:28 ` Paolo Bonzini [this message]
2022-05-25 19:28 ` [PULL 02/17] hostmem: default the amount of prealloc-threads to smp-cpus Paolo Bonzini
2022-05-25 19:28 ` [PULL 03/17] thread-pool: optimize scheduling of completion bottom half Paolo Bonzini
2022-05-25 19:28 ` [PULL 04/17] thread-pool: replace semaphore with condition variable Paolo Bonzini
2022-05-25 19:28 ` [PULL 05/17] thread-pool: remove stopping variable Paolo Bonzini
2022-05-25 19:28 ` [PULL 06/17] contrib/elf2dmp: add ELF dump header checking Paolo Bonzini
2022-05-25 19:28 ` [PULL 07/17] hw/audio/ac97: Coding style fixes to avoid checkpatch errors Paolo Bonzini
2022-05-25 19:28 ` [PULL 08/17] hw/audio/ac97: Remove unimplemented reset functions Paolo Bonzini
2022-05-25 19:28 ` [PULL 09/17] hw/audio/ac97: Remove unneeded local variables Paolo Bonzini
2022-05-25 19:28 ` [PULL 10/17] target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host Paolo Bonzini
2022-05-25 19:28 ` [PULL 11/17] ide_ioport_read: Return lower octet of data register instead of 0xFF Paolo Bonzini
2022-05-25 19:28 ` [PULL 12/17] i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES Paolo Bonzini
2022-05-25 19:28 ` [PULL 13/17] i386: Hyper-V Enlightened MSR bitmap feature Paolo Bonzini
2022-05-25 19:28 ` [PULL 14/17] i386: Hyper-V XMM fast hypercall input feature Paolo Bonzini
2022-05-25 19:28 ` [PULL 15/17] i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls Paolo Bonzini
2022-05-25 19:28 ` [PULL 16/17] i386: Hyper-V Direct TLB flush hypercall Paolo Bonzini
2022-05-25 19:28 ` [PULL 17/17] i386: docs: Convert hyperv.txt to rST Paolo Bonzini
2022-05-25 22:20 ` [PULL 00/17] Misc patches for 2022-05-25 Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220525192852.301633-2-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=weijiang.yang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).