From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
Nicholas Piggin <npiggin@gmail.com>
Subject: [PULL 26/34] target/ppc: Implement lwsync with weaker memory ordering
Date: Thu, 26 May 2022 18:38:07 -0300 [thread overview]
Message-ID: <20220526213815.92701-27-danielhb413@gmail.com> (raw)
In-Reply-To: <20220526213815.92701-1-danielhb413@gmail.com>
From: Nicholas Piggin <npiggin@gmail.com>
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 4 +++-
target/ppc/cpu_init.c | 13 +++++++------
target/ppc/machine.c | 3 ++-
target/ppc/translate.c | 8 +++++++-
4 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 901ded79e9..bf8f8aad2c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2273,6 +2273,8 @@ enum {
PPC2_ISA300 = 0x0000000000080000ULL,
/* POWER ISA 3.1 */
PPC2_ISA310 = 0x0000000000100000ULL,
+ /* lwsync instruction */
+ PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2281,7 +2283,7 @@ enum {
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
- PPC2_ISA300 | PPC2_ISA310)
+ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC)
};
/*****************************************************************************/
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 527ad40fcb..0f891afa04 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5769,7 +5769,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC2_FP_CVT_S64;
+ pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_VR) |
(1ull << MSR_POW) |
@@ -5846,7 +5846,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
PPC_64B |
PPC_POPCNTB |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC2_FP_CVT_S64;
+ pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_VR) |
(1ull << MSR_POW) |
@@ -5985,7 +5985,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
- PPC2_PM_ISA206;
+ PPC2_PM_ISA206 | PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -6159,7 +6159,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_PM_ISA206;
+ PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
@@ -6379,7 +6379,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
@@ -6596,7 +6596,8 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
+ PPC2_MEM_LWSYNC;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 7104a5c67e..a7d9036c09 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -157,7 +157,8 @@ static int cpu_pre_save(void *opaque)
| PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
| PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
| PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
- | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
+ | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM
+ | PPC2_MEM_LWSYNC;
env->spr[SPR_LR] = env->lr;
env->spr[SPR_CTR] = env->ctr;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eb42f7e459..1d6daa4608 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4041,8 +4041,13 @@ static void gen_stqcx_(DisasContext *ctx)
/* sync */
static void gen_sync(DisasContext *ctx)
{
+ TCGBar bar = TCG_MO_ALL;
uint32_t l = (ctx->opcode >> 21) & 3;
+ if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
+ bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
+ }
+
/*
* We may need to check for a pending TLB flush.
*
@@ -4054,7 +4059,8 @@ static void gen_sync(DisasContext *ctx)
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true);
}
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+
+ tcg_gen_mb(bar | TCG_BAR_SC);
}
/* wait */
--
2.36.1
next prev parent reply other threads:[~2022-05-26 22:13 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-26 21:37 [PULL 00/34] ppc queue Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 01/34] pseries: allow setting stdout-path even on machines with a VGA Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 02/34] hw/ppc/e500: Remove unused BINARY_DEVICE_TREE_FILE Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 03/34] spapr: Use address from elf parser for kernel address Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 04/34] spapr/docs: Add a few words about x-vof Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 05/34] mos6522: fix linking error when CONFIG_MOS6522 is not set Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 06/34] target/ppc: Fix tlbie Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 07/34] target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 08/34] target/ppc: Fix FPSCR.FI changing in float_overflow_excp() Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 09/34] target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 10/34] pnv/xive2: Don't overwrite PC registers when writing TCTXT registers Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 11/34] target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 12/34] target/ppc: use TCG_CALL_NO_RWG in vector helpers without env Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 13/34] target/ppc: use TCG_CALL_NO_RWG in BCD helpers Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 14/34] target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 15/34] target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 16/34] target/ppc: declare xscvspdpn helper with call flags Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 17/34] target/ppc: declare xvxsigsp " Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 19/34] target/ppc: introduce do_va_helper Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 20/34] target/ppc: declare vmsum[um]bm helpers with call flags Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 21/34] target/ppc: declare vmsumuh[ms] helper " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 22/34] target/ppc: declare vmsumsh[ms] " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 23/34] target/ppc: Fix eieio memory ordering semantics Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 24/34] tcg/ppc: ST_ST memory ordering is not provided with eieio Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 25/34] tcg/ppc: Optimize memory ordering generation with lwsync Daniel Henrique Barboza
2022-05-26 21:38 ` Daniel Henrique Barboza [this message]
2022-05-26 21:38 ` [PULL 27/34] target/ppc: Implement xxm[tf]acc and xxsetaccz Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 28/34] target/ppc: Implemented xvi*ger* instructions Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 30/34] target/ppc: Implemented xvf*ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 31/34] target/ppc: Implemented xvf16ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 32/34] target/ppc: Implemented pmxvf*ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 33/34] target/ppc: Implemented [pm]xvbf16ger2* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 34/34] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap Daniel Henrique Barboza
2022-05-27 15:19 ` [PULL 00/34] ppc queue Richard Henderson
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