From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: laurent@vivier.eu
Subject: [PATCH v5 14/17] tests/tcg/m68k: Add trap.c
Date: Fri, 27 May 2022 09:48:04 -0700 [thread overview]
Message-ID: <20220527164807.135038-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org>
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/m68k/trap.c | 129 +++++++++++++++++++++++++++++++++
tests/tcg/m68k/Makefile.target | 3 +
2 files changed, 132 insertions(+)
create mode 100644 tests/tcg/m68k/trap.c
diff --git a/tests/tcg/m68k/trap.c b/tests/tcg/m68k/trap.c
new file mode 100644
index 0000000000..96cac18d4d
--- /dev/null
+++ b/tests/tcg/m68k/trap.c
@@ -0,0 +1,129 @@
+/*
+ * Test m68k trap addresses.
+ */
+
+#define _GNU_SOURCE 1
+#include <signal.h>
+#include <assert.h>
+#include <limits.h>
+
+static int expect_sig;
+static int expect_si_code;
+static void *expect_si_addr;
+static greg_t expect_mc_pc;
+static volatile int got_signal;
+
+static void sig_handler(int sig, siginfo_t *si, void *puc)
+{
+ ucontext_t *uc = puc;
+ mcontext_t *mc = &uc->uc_mcontext;
+
+ assert(sig == expect_sig);
+ assert(si->si_code == expect_si_code);
+ assert(si->si_addr == expect_si_addr);
+ assert(mc->gregs[R_PC] == expect_mc_pc);
+
+ got_signal = 1;
+}
+
+#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc)
+#define FMT0_STR(S) \
+ "move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
+#define FMT2_STR(S) \
+ "move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
+
+#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0)
+
+int main(int argc, char **argv)
+{
+ struct sigaction act = {
+ .sa_sigaction = sig_handler,
+ .sa_flags = SA_SIGINFO
+ };
+ int t0, t1;
+
+ sigaction(SIGILL, &act, NULL);
+ sigaction(SIGTRAP, &act, NULL);
+ sigaction(SIGFPE, &act, NULL);
+
+ expect_sig = SIGFPE;
+ expect_si_code = FPE_INTOVF;
+ asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS);
+ CHECK_SIG;
+
+#if 0
+ /* FIXME: chk2 not correctly translated. */
+ int bounds[2] = { 0, 1 };
+ asm volatile(FMT2_STR("0:\tchk2.l %0, %1")
+ : : "m"(bounds), "d"(2), FMT_INS);
+ CHECK_SIG;
+#endif
+
+ asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv")
+ : : "d"(INT_MIN), "d"(1), FMT_INS);
+ CHECK_SIG;
+
+ asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq")
+ : : "d"(0), FMT_INS);
+ CHECK_SIG;
+
+ asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234")
+ : : "d"(0), FMT_INS);
+ CHECK_SIG;
+
+ asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678")
+ : : "d"(0), FMT_INS);
+ CHECK_SIG;
+
+ asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq")
+ : : "f"(0.0L), FMT_INS);
+ CHECK_SIG;
+
+ expect_si_code = FPE_INTDIV;
+
+ asm volatile(FMT2_STR("0:\tdivs.w %1, %0")
+ : "=d"(t0) : "d"(0), "0"(1), FMT_INS);
+ CHECK_SIG;
+
+ asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0")
+ : "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS);
+ CHECK_SIG;
+
+ expect_sig = SIGILL;
+ expect_si_code = ILL_ILLTRP;
+ asm volatile(FMT0_STR("trap #1") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #2") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #3") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #4") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #5") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #6") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #7") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #8") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #9") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #10") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #11") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #12") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #13") : : FMT_INS);
+ CHECK_SIG;
+ asm volatile(FMT0_STR("trap #14") : : FMT_INS);
+ CHECK_SIG;
+
+ expect_sig = SIGTRAP;
+ expect_si_code = TRAP_BRKPT;
+ asm volatile(FMT0_STR("trap #15") : : FMT_INS);
+ CHECK_SIG;
+
+ return 0;
+}
diff --git a/tests/tcg/m68k/Makefile.target b/tests/tcg/m68k/Makefile.target
index 62f109eef4..1163c7ef03 100644
--- a/tests/tcg/m68k/Makefile.target
+++ b/tests/tcg/m68k/Makefile.target
@@ -3,5 +3,8 @@
# m68k specific tweaks - specifically masking out broken tests
#
+VPATH += $(SRC_PATH)/tests/tcg/m68k
+TESTS += trap
+
# On m68k Linux supports 4k and 8k pages (but 8k is currently broken)
EXTRA_RUNS+=run-test-mmap-4096 # run-test-mmap-8192
--
2.34.1
next prev parent reply other threads:[~2022-05-27 17:10 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-27 16:47 [PATCH v5 00/17] target/m68k: Conditional traps + trap cleanup Richard Henderson
2022-05-27 16:47 ` [PATCH v5 01/17] target/m68k: Raise the TRAPn exception with the correct pc Richard Henderson
2022-05-27 16:47 ` [PATCH v5 02/17] target/m68k: Switch over exception type in m68k_interrupt_all Richard Henderson
2022-05-27 16:47 ` [PATCH v5 03/17] target/m68k: Fix coding style " Richard Henderson
2022-05-27 16:47 ` [PATCH v5 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15 Richard Henderson
2022-05-28 16:33 ` Laurent Vivier
2022-05-27 16:47 ` [PATCH v5 05/17] target/m68k: Remove retaddr in m68k_interrupt_all Richard Henderson
2022-05-27 16:47 ` [PATCH v5 06/17] target/m68k: Fix address argument for EXCP_CHK Richard Henderson
2022-05-27 16:47 ` [PATCH v5 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 Richard Henderson
2022-05-27 16:47 ` [PATCH v5 08/17] target/m68k: Fix address argument for EXCP_TRACE Richard Henderson
2022-05-27 16:47 ` [PATCH v5 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL Richard Henderson
2022-05-27 16:48 ` [PATCH v5 10/17] target/m68k: Implement TRAPcc Richard Henderson
2022-05-31 8:01 ` Laurent Vivier
2022-05-31 14:59 ` Richard Henderson
2022-05-31 18:05 ` Laurent Vivier
2022-05-31 21:14 ` Richard Henderson
2022-05-27 16:48 ` [PATCH v5 11/17] target/m68k: Implement TPF in terms of TRAPcc Richard Henderson
2022-05-27 16:48 ` [PATCH v5 12/17] target/m68k: Implement TRAPV Richard Henderson
2022-05-27 16:48 ` [PATCH v5 13/17] target/m68k: Implement FTRAPcc Richard Henderson
2022-05-27 16:48 ` Richard Henderson [this message]
2022-05-27 16:48 ` [PATCH v5 15/17] linux-user/strace: Use is_error in print_syscall_err Richard Henderson
2022-05-28 16:34 ` Laurent Vivier
2022-05-27 16:48 ` [PATCH v5 16/17] linux-user/strace: Adjust get_thread_area for m68k Richard Henderson
2022-05-27 16:48 ` [PATCH v5 17/17] target/m68k: Mark helper_raise_exception as noreturn Richard Henderson
2022-05-28 16:36 ` [PATCH v5 00/17] target/m68k: Conditional traps + trap cleanup Laurent Vivier
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