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Tsirkin" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: Lev Kujawski , qemu-trival@nongnu.org, John Snow , "open list:IDE" , =?iso-8859-1?Q?Herv=E9?= Poussineau , Bernhard Beschow , "open list:All patches CC here" Subject: Re: [PATCH 4/4] hw/ide/piix: Ignore writes of hardwired PCI command register bits Message-ID: <20220530140956-mutt-send-email-mst@kernel.org> References: <20220528204702.167912-1-lkujaw@member.fsf.org> <20220528204702.167912-4-lkujaw@member.fsf.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, May 30, 2022 at 03:33:18PM +0200, Philippe Mathieu-Daudé wrote: > On 28/5/22 22:47, Lev Kujawski wrote: > > One method to enable PCI bus mastering for IDE controllers, often used > > by x86 firmware, is to write 0x7 to the PCI command register. Neither > > the PIIX3 specification nor actual hardware (a Tyan S1686D system) > > permit modification of the Memory Space Enable (MSE) bit, 1, and thus > > the command register would be left in an unspecified state without > > this patch. > > > > Signed-off-by: Lev Kujawski > > --- > > hw/ide/piix.c | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/hw/ide/piix.c b/hw/ide/piix.c > > index 76ea8fd9f6..f1d1168ecd 100644 > > --- a/hw/ide/piix.c > > +++ b/hw/ide/piix.c > > @@ -25,6 +25,8 @@ > > * References: > > * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR, > > * 290550-002, Intel Corporation, April 1997. > > + * [2] 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4), 290562-001, > > + * Intel Corporation, April 1997. > > */ > > #include "qemu/osdep.h" > > @@ -32,6 +34,7 @@ > > #include "migration/vmstate.h" > > #include "qapi/error.h" > > #include "qemu/module.h" > > +#include "qemu/range.h" > > #include "sysemu/block-backend.h" > > #include "sysemu/blockdev.h" > > #include "sysemu/dma.h" > > @@ -220,6 +223,26 @@ static void pci_piix_ide_exitfn(PCIDevice *dev) > > } > > } > > +static void piix_pci_config_write(PCIDevice *d, uint32_t addr, > > + uint32_t val, int l) > > +{ > > + /* > > + * Mask all IDE PCI command register bits except for Bus Master > > + * Function Enable (bit 2) and I/O Space Enable (bit 1), as the > > + * remainder are hardwired to 0 [1, p.48] [2, p.89-90]. > > + * > > + * NOTE: According to the PIIX3 datasheet [1], the Memory Space > > + * Enable (MSE bit) is hardwired to 1, but this is contradicted by > > + * actual PIIX3 hardware, the datasheet itself (viz., Default > > + * Value: 0000h), and the PIIX4 datasheet [2]. > > + */ > > + if (range_covers_byte(addr, l, PCI_COMMAND)) { > > + val &= ~(0xfffa << ((PCI_COMMAND - addr) << 3)); > > Watch out, len can be 1/2/4. If there are bits hardwired to 0 the right way to do it is by clearing a bit in wmask. Might need machine compat machinery for this. > > + } > > + > > + pci_default_write_config(d, addr, val, l); > > +} > > + > > /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ > > static void piix3_ide_class_init(ObjectClass *klass, void *data) > > { > > @@ -232,6 +255,7 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) > > k->vendor_id = PCI_VENDOR_ID_INTEL; > > k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; > > k->class_id = PCI_CLASS_STORAGE_IDE; > > + k->config_write = piix_pci_config_write; > > set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); > > dc->hotpluggable = false; > > } > > @@ -260,6 +284,7 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) > > k->vendor_id = PCI_VENDOR_ID_INTEL; > > k->device_id = PCI_DEVICE_ID_INTEL_82371AB; > > k->class_id = PCI_CLASS_STORAGE_IDE; > > + k->config_write = piix_pci_config_write; > > set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); > > dc->hotpluggable = false; > > }