From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 020/117] target/arm: Use TRANS_FEAT for do_sve2_zzw_data
Date: Mon, 30 May 2022 17:05:31 +0100 [thread overview]
Message-ID: <20220530160708.726466-21-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220530160708.726466-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Convert SVE translation functions using do_sve2_zzw_data
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-18-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 297 ++++++++++++++++++-------------------
1 file changed, 145 insertions(+), 152 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index c345399ace9..2347b60d8ef 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6711,79 +6711,99 @@ DO_SVE2_ZPZZ(USQADD, usqadd)
* SVE2 Widening Integer Arithmetic
*/
-static bool do_sve2_zzw_ool(DisasContext *s, arg_rrr_esz *a,
- gen_helper_gvec_3 *fn, int data)
-{
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
- return false;
- }
- if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vec_full_reg_offset(s, a->rm),
- vsz, vsz, data, fn);
- }
- return true;
-}
+static gen_helper_gvec_3 * const saddl_fns[4] = {
+ NULL, gen_helper_sve2_saddl_h,
+ gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d,
+};
+TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ saddl_fns[a->esz], a, 0)
+TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ saddl_fns[a->esz], a, 3)
+TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ saddl_fns[a->esz], a, 2)
-#define DO_SVE2_ZZZ_TB(NAME, name, SEL1, SEL2) \
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
-{ \
- static gen_helper_gvec_3 * const fns[4] = { \
- NULL, gen_helper_sve2_##name##_h, \
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
- }; \
- return do_sve2_zzw_ool(s, a, fns[a->esz], (SEL2 << 1) | SEL1); \
-}
+static gen_helper_gvec_3 * const ssubl_fns[4] = {
+ NULL, gen_helper_sve2_ssubl_h,
+ gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d,
+};
+TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ ssubl_fns[a->esz], a, 0)
+TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ ssubl_fns[a->esz], a, 3)
+TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ ssubl_fns[a->esz], a, 2)
+TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ ssubl_fns[a->esz], a, 1)
-DO_SVE2_ZZZ_TB(SADDLB, saddl, false, false)
-DO_SVE2_ZZZ_TB(SSUBLB, ssubl, false, false)
-DO_SVE2_ZZZ_TB(SABDLB, sabdl, false, false)
+static gen_helper_gvec_3 * const sabdl_fns[4] = {
+ NULL, gen_helper_sve2_sabdl_h,
+ gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d,
+};
+TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sabdl_fns[a->esz], a, 0)
+TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sabdl_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(UADDLB, uaddl, false, false)
-DO_SVE2_ZZZ_TB(USUBLB, usubl, false, false)
-DO_SVE2_ZZZ_TB(UABDLB, uabdl, false, false)
+static gen_helper_gvec_3 * const uaddl_fns[4] = {
+ NULL, gen_helper_sve2_uaddl_h,
+ gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d,
+};
+TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ uaddl_fns[a->esz], a, 0)
+TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ uaddl_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(SADDLT, saddl, true, true)
-DO_SVE2_ZZZ_TB(SSUBLT, ssubl, true, true)
-DO_SVE2_ZZZ_TB(SABDLT, sabdl, true, true)
+static gen_helper_gvec_3 * const usubl_fns[4] = {
+ NULL, gen_helper_sve2_usubl_h,
+ gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d,
+};
+TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ usubl_fns[a->esz], a, 0)
+TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ usubl_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(UADDLT, uaddl, true, true)
-DO_SVE2_ZZZ_TB(USUBLT, usubl, true, true)
-DO_SVE2_ZZZ_TB(UABDLT, uabdl, true, true)
+static gen_helper_gvec_3 * const uabdl_fns[4] = {
+ NULL, gen_helper_sve2_uabdl_h,
+ gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d,
+};
+TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
+ uabdl_fns[a->esz], a, 0)
+TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
+ uabdl_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true)
-DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true)
-DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false)
+static gen_helper_gvec_3 * const sqdmull_fns[4] = {
+ NULL, gen_helper_sve2_sqdmull_zzz_h,
+ gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d,
+};
+TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sqdmull_fns[a->esz], a, 0)
+TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sqdmull_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false)
-DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true)
+static gen_helper_gvec_3 * const smull_fns[4] = {
+ NULL, gen_helper_sve2_smull_zzz_h,
+ gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d,
+};
+TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ smull_fns[a->esz], a, 0)
+TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ smull_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false)
-DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
+static gen_helper_gvec_3 * const umull_fns[4] = {
+ NULL, gen_helper_sve2_umull_zzz_h,
+ gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d,
+};
+TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ umull_fns[a->esz], a, 0)
+TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
+ umull_fns[a->esz], a, 3)
-DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
-DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
-
-static bool do_eor_tb(DisasContext *s, arg_rrr_esz *a, bool sel1)
-{
- static gen_helper_gvec_3 * const fns[4] = {
- gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
- gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
- };
- return do_sve2_zzw_ool(s, a, fns[a->esz], (!sel1 << 1) | sel1);
-}
-
-static bool trans_EORBT(DisasContext *s, arg_rrr_esz *a)
-{
- return do_eor_tb(s, a, false);
-}
-
-static bool trans_EORTB(DisasContext *s, arg_rrr_esz *a)
-{
- return do_eor_tb(s, a, true);
-}
+static gen_helper_gvec_3 * const eoril_fns[4] = {
+ gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
+ gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
+};
+TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2)
+TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1)
static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
{
@@ -6794,38 +6814,39 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) {
return false;
}
- return do_sve2_zzw_ool(s, a, fns[a->esz], sel);
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
}
-static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a)
-{
- return do_trans_pmull(s, a, false);
-}
+TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
+TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
-static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a)
-{
- return do_trans_pmull(s, a, true);
-}
+static gen_helper_gvec_3 * const saddw_fns[4] = {
+ NULL, gen_helper_sve2_saddw_h,
+ gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d,
+};
+TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0)
+TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1)
-#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
-{ \
- static gen_helper_gvec_3 * const fns[4] = { \
- NULL, gen_helper_sve2_##name##_h, \
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
- }; \
- return do_sve2_zzw_ool(s, a, fns[a->esz], SEL2); \
-}
+static gen_helper_gvec_3 * const ssubw_fns[4] = {
+ NULL, gen_helper_sve2_ssubw_h,
+ gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d,
+};
+TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0)
+TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1)
-DO_SVE2_ZZZ_WTB(SADDWB, saddw, false)
-DO_SVE2_ZZZ_WTB(SADDWT, saddw, true)
-DO_SVE2_ZZZ_WTB(SSUBWB, ssubw, false)
-DO_SVE2_ZZZ_WTB(SSUBWT, ssubw, true)
+static gen_helper_gvec_3 * const uaddw_fns[4] = {
+ NULL, gen_helper_sve2_uaddw_h,
+ gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d,
+};
+TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0)
+TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1)
-DO_SVE2_ZZZ_WTB(UADDWB, uaddw, false)
-DO_SVE2_ZZZ_WTB(UADDWT, uaddw, true)
-DO_SVE2_ZZZ_WTB(USUBWB, usubw, false)
-DO_SVE2_ZZZ_WTB(USUBWT, usubw, true)
+static gen_helper_gvec_3 * const usubw_fns[4] = {
+ NULL, gen_helper_sve2_usubw_h,
+ gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d,
+};
+TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0)
+TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1)
static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm)
{
@@ -6986,72 +7007,44 @@ static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a)
return do_sve2_shll_tb(s, a, true, true);
}
-static bool trans_BEXT(DisasContext *s, arg_rrr_esz *a)
-{
- static gen_helper_gvec_3 * const fns[4] = {
- gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
- gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
- };
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
- return false;
- }
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
-}
+static gen_helper_gvec_3 * const bext_fns[4] = {
+ gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
+ gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
+};
+TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bext_fns[a->esz], a, 0)
-static bool trans_BDEP(DisasContext *s, arg_rrr_esz *a)
-{
- static gen_helper_gvec_3 * const fns[4] = {
- gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
- gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
- };
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
- return false;
- }
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
-}
+static gen_helper_gvec_3 * const bdep_fns[4] = {
+ gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
+ gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
+};
+TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bdep_fns[a->esz], a, 0)
-static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a)
-{
- static gen_helper_gvec_3 * const fns[4] = {
- gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
- gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
- };
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
- return false;
- }
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
-}
+static gen_helper_gvec_3 * const bgrp_fns[4] = {
+ gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
+ gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
+};
+TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bgrp_fns[a->esz], a, 0)
-static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot)
-{
- static gen_helper_gvec_3 * const fns[2][4] = {
- { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
- gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d },
- { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
- gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d },
- };
- return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot);
-}
+static gen_helper_gvec_3 * const cadd_fns[4] = {
+ gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
+ gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d,
+};
+TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
+ cadd_fns[a->esz], a, 0)
+TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
+ cadd_fns[a->esz], a, 1)
-static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a)
-{
- return do_cadd(s, a, false, false);
-}
-
-static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a)
-{
- return do_cadd(s, a, false, true);
-}
-
-static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a)
-{
- return do_cadd(s, a, true, false);
-}
-
-static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
-{
- return do_cadd(s, a, true, true);
-}
+static gen_helper_gvec_3 * const sqcadd_fns[4] = {
+ gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
+ gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d,
+};
+TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sqcadd_fns[a->esz], a, 0)
+TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
+ sqcadd_fns[a->esz], a, 1)
static gen_helper_gvec_4 * const sabal_fns[4] = {
NULL, gen_helper_sve2_sabal_h,
--
2.25.1
next prev parent reply other threads:[~2022-05-30 16:31 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-30 16:05 [PULL 000/117] target-arm queue Peter Maydell
2022-05-30 16:05 ` [PULL 001/117] docs/system/arm: Add FEAT_HCX to list of emulated features Peter Maydell
2022-05-30 16:05 ` [PULL 002/117] target/arm/hvf: Include missing "cpregs.h" Peter Maydell
2022-05-30 16:05 ` [PULL 003/117] hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready Peter Maydell
2022-05-30 16:05 ` [PULL 004/117] target/arm: Introduce TRANS, TRANS_FEAT Peter Maydell
2022-05-30 16:05 ` [PULL 005/117] target/arm: Move null function and sve check into gen_gvec_ool_zz Peter Maydell
2022-05-30 16:05 ` [PULL 006/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz Peter Maydell
2022-05-30 16:05 ` [PULL 007/117] target/arm: Move null function and sve check into gen_gvec_ool_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 008/117] target/arm: Introduce gen_gvec_ool_arg_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 009/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 010/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool Peter Maydell
2022-05-30 16:05 ` [PULL 011/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 012/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 013/117] target/arm: Introduce gen_gvec_ool_arg_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 014/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool Peter Maydell
2022-05-30 16:05 ` [PULL 015/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 016/117] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz Peter Maydell
2022-05-30 16:05 ` [PULL 017/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz Peter Maydell
2022-05-30 16:05 ` [PULL 018/117] target/arm: Use TRANS_FEAT for do_sve2_zzz_data Peter Maydell
2022-05-30 16:05 ` [PULL 019/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data Peter Maydell
2022-05-30 16:05 ` Peter Maydell [this message]
2022-05-30 16:05 ` [PULL 021/117] target/arm: Use TRANS_FEAT for USDOT_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 022/117] target/arm: Move null function and sve check into gen_gvec_ool_zzp Peter Maydell
2022-05-30 16:05 ` [PULL 023/117] target/arm: Introduce gen_gvec_ool_arg_zpz Peter Maydell
2022-05-30 16:05 ` [PULL 024/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz Peter Maydell
2022-05-30 16:05 ` [PULL 025/117] target/arm: Use TRANS_FEAT for do_sve2_zpz_data Peter Maydell
2022-05-30 16:05 ` [PULL 026/117] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi Peter Maydell
2022-05-30 16:05 ` [PULL 027/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi Peter Maydell
2022-05-30 16:05 ` [PULL 028/117] target/arm: Move null function and sve check into gen_gvec_ool_zzzp Peter Maydell
2022-05-30 16:05 ` [PULL 029/117] target/arm: Introduce gen_gvec_ool_arg_zpzz Peter Maydell
2022-05-30 16:05 ` [PULL 030/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz Peter Maydell
2022-05-30 16:05 ` [PULL 031/117] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool Peter Maydell
2022-05-30 16:05 ` [PULL 032/117] target/arm: Merge gen_gvec_fn_zz into do_mov_z Peter Maydell
2022-05-30 16:05 ` [PULL 033/117] target/arm: Move null function and sve check into gen_gvec_fn_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 034/117] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 035/117] target/arm: More use of gen_gvec_fn_arg_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 036/117] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 037/117] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz Peter Maydell
2022-05-30 16:05 ` [PULL 038/117] target/arm: Use TRANS_FEAT for RAX1 Peter Maydell
2022-05-30 16:05 ` [PULL 039/117] target/arm: Introduce gen_gvec_fn_arg_zzzz Peter Maydell
2022-05-30 16:05 ` [PULL 040/117] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn Peter Maydell
2022-05-30 16:05 ` [PULL 041/117] target/arm: Introduce gen_gvec_fn_zzi Peter Maydell
2022-05-30 16:05 ` [PULL 042/117] target/arm: Use TRANS_FEAT for do_zz_dbm Peter Maydell
2022-05-30 16:05 ` [PULL 043/117] target/arm: Hoist sve access check through do_sel_z Peter Maydell
2022-05-30 16:05 ` [PULL 044/117] target/arm: Introduce gen_gvec_fn_arg_zzi Peter Maydell
2022-05-30 16:05 ` [PULL 045/117] target/arm: Use TRANS_FEAT for do_sve2_fn2i Peter Maydell
2022-05-30 16:05 ` [PULL 046/117] target/arm: Use TRANS_FEAT for do_vpz_ool Peter Maydell
2022-05-30 16:05 ` [PULL 047/117] target/arm: Use TRANS_FEAT for do_shift_imm Peter Maydell
2022-05-30 16:05 ` [PULL 048/117] target/arm: Introduce do_shift_zpzi Peter Maydell
2022-05-30 16:06 ` [PULL 049/117] target/arm: Use TRANS_FEAT for do_shift_zpzi Peter Maydell
2022-05-30 16:06 ` [PULL 050/117] target/arm: Use TRANS_FEAT for do_zpzzz_ool Peter Maydell
2022-05-30 16:06 ` [PULL 051/117] target/arm: Move sve check into do_index Peter Maydell
2022-05-30 16:06 ` [PULL 052/117] target/arm: Use TRANS_FEAT for do_index Peter Maydell
2022-05-30 16:06 ` [PULL 053/117] target/arm: Use TRANS_FEAT for do_adr Peter Maydell
2022-05-30 16:06 ` [PULL 054/117] target/arm: Use TRANS_FEAT for do_predset Peter Maydell
2022-05-30 16:06 ` [PULL 055/117] target/arm: Use TRANS_FEAT for RDFFR, WRFFR Peter Maydell
2022-05-30 16:06 ` [PULL 056/117] target/arm: Use TRANS_FEAT for do_pfirst_pnext Peter Maydell
2022-05-30 16:06 ` [PULL 057/117] target/arm: Use TRANS_FEAT for do_EXT Peter Maydell
2022-05-30 16:06 ` [PULL 058/117] target/arm: Use TRANS_FEAT for do_perm_pred3 Peter Maydell
2022-05-30 16:06 ` [PULL 059/117] target/arm: Use TRANS_FEAT for do_perm_pred2 Peter Maydell
2022-05-30 16:06 ` [PULL 060/117] target/arm: Move sve zip high_ofs into simd_data Peter Maydell
2022-05-30 16:06 ` [PULL 061/117] target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q Peter Maydell
2022-05-30 16:06 ` [PULL 062/117] target/arm: Use TRANS_FEAT " Peter Maydell
2022-05-30 16:06 ` [PULL 063/117] target/arm: Use TRANS_FEAT for do_clast_vector Peter Maydell
2022-05-30 16:06 ` [PULL 064/117] target/arm: Use TRANS_FEAT for do_clast_fp Peter Maydell
2022-05-30 16:06 ` [PULL 065/117] target/arm: Use TRANS_FEAT for do_clast_general Peter Maydell
2022-05-30 16:06 ` [PULL 066/117] target/arm: Use TRANS_FEAT for do_last_fp Peter Maydell
2022-05-30 16:06 ` [PULL 067/117] target/arm: Use TRANS_FEAT for do_last_general Peter Maydell
2022-05-30 16:06 ` [PULL 068/117] target/arm: Use TRANS_FEAT for SPLICE Peter Maydell
2022-05-30 16:06 ` [PULL 069/117] target/arm: Use TRANS_FEAT for do_ppzz_flags Peter Maydell
2022-05-30 16:06 ` [PULL 070/117] target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags Peter Maydell
2022-05-30 16:06 ` [PULL 071/117] target/arm: Use TRANS_FEAT for do_ppzi_flags Peter Maydell
2022-05-30 16:06 ` [PULL 072/117] target/arm: Use TRANS_FEAT for do_brk2, do_brk3 Peter Maydell
2022-05-30 16:06 ` [PULL 073/117] target/arm: Use TRANS_FEAT for MUL_zzi Peter Maydell
2022-05-30 16:06 ` [PULL 074/117] target/arm: Reject dup_i w/ shifted byte early Peter Maydell
2022-05-30 16:06 ` [PULL 075/117] target/arm: Reject add/sub " Peter Maydell
2022-05-30 16:06 ` [PULL 076/117] target/arm: Reject copy " Peter Maydell
2022-05-30 16:06 ` [PULL 077/117] target/arm: Use TRANS_FEAT for ADD_zzi Peter Maydell
2022-05-30 16:06 ` [PULL 078/117] target/arm: Use TRANS_FEAT for do_zzi_sat Peter Maydell
2022-05-30 16:06 ` [PULL 079/117] target/arm: Use TRANS_FEAT for do_zzi_ool Peter Maydell
2022-05-30 16:06 ` [PULL 080/117] target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz Peter Maydell
2022-05-30 16:06 ` [PULL 081/117] target/arm: Use TRANS_FEAT for FMMLA Peter Maydell
2022-05-30 16:06 ` [PULL 082/117] target/arm: Move sve check into gen_gvec_fn_ppp Peter Maydell
2022-05-30 16:06 ` [PULL 083/117] target/arm: Implement NOT (prediates) alias Peter Maydell
2022-05-30 16:06 ` [PULL 084/117] target/arm: Use TRANS_FEAT for SEL_zpzz Peter Maydell
2022-05-30 16:06 ` [PULL 085/117] target/arm: Use TRANS_FEAT for MOVPRFX Peter Maydell
2022-05-30 16:06 ` [PULL 086/117] target/arm: Use TRANS_FEAT for FMLA Peter Maydell
2022-05-30 16:06 ` [PULL 087/117] target/arm: Use TRANS_FEAT for BFMLA Peter Maydell
2022-05-30 16:06 ` [PULL 088/117] target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz Peter Maydell
2022-05-30 16:06 ` [PULL 089/117] target/arm: Use TRANS_FEAT for DO_FP3 Peter Maydell
2022-05-30 16:06 ` [PULL 090/117] target/arm: Use TRANS_FEAT for FMUL_zzx Peter Maydell
2022-05-30 16:06 ` [PULL 091/117] target/arm: Use TRANS_FEAT for FTMAD Peter Maydell
2022-05-30 16:06 ` [PULL 092/117] target/arm: Move null function and sve check into do_reduce Peter Maydell
2022-05-30 16:06 ` [PULL 093/117] target/arm: Use TRANS_FEAT for do_reduce Peter Maydell
2022-05-30 16:06 ` [PULL 094/117] target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE Peter Maydell
2022-05-30 16:06 ` [PULL 095/117] target/arm: Expand frint_fns for MO_8 Peter Maydell
2022-05-30 16:06 ` [PULL 096/117] target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz Peter Maydell
2022-05-30 16:06 ` [PULL 097/117] target/arm: Move null function and sve check into do_frint_mode Peter Maydell
2022-05-30 16:06 ` [PULL 098/117] target/arm: Use TRANS_FEAT for do_frint_mode Peter Maydell
2022-05-30 16:06 ` [PULL 099/117] target/arm: Use TRANS_FEAT for FLOGB Peter Maydell
2022-05-30 19:39 ` [PULL 000/117] target-arm queue Richard Henderson
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