From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 2/3] tcg/i386: Fix encoding of OPC_VPSRAQ for INDEX_op_sars_vec
Date: Thu, 2 Jun 2022 08:13:11 -0700 [thread overview]
Message-ID: <20220602151312.477967-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220602151312.477967-1-richard.henderson@linaro.org>
We wanted the VPSRAQ variant with the scalar vector shift operand,
not the variant with an immediate operand.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1022
Fixes: 47b331b2a8da ("tcg/i386: Implement avx512 scalar shift")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index b5c6159853..d52206ba4d 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -375,7 +375,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16)
#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16)
#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16)
-#define OPC_VPSRAQ (0x72 | P_EXT | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSRAQ (0xe2 | P_EXT | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16)
#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16)
#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16)
--
2.34.1
next prev parent reply other threads:[~2022-06-02 15:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-02 15:13 [PULL 0/3] tcg patch queue Richard Henderson
2022-06-02 15:13 ` [PULL 1/3] tcg: Add tcg_gen_mov_ptr Richard Henderson
2022-06-02 15:13 ` Richard Henderson [this message]
2022-06-02 15:13 ` [PULL 3/3] tcg/aarch64: Fix illegal insn from out-of-range shli Richard Henderson
2022-06-02 16:41 ` [PULL 0/3] tcg patch queue Richard Henderson
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