From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =gaosong@loongson.cn, yangxiaojuan@loongson.cn,
Song Gao <gaosong@loongson.cn>
Subject: [PULL 14/43] target/loongarch: Add floating point load/store instruction translation
Date: Mon, 6 Jun 2022 16:14:21 -0700 [thread overview]
Message-ID: <20220606231450.448443-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220606231450.448443-1-richard.henderson@linaro.org>
From: Song Gao <gaosong@loongson.cn>
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-15-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insns.decode | 24 +++
target/loongarch/translate.c | 1 +
.../loongarch/insn_trans/trans_fmemory.c.inc | 153 ++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_fmemory.c.inc
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index c62a4f6dcd..8f286e7233 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -36,6 +36,8 @@
&fc fd cj
&cr cd rj
&rc rd cj
+&frr fd rj rk
+&fr_i fd rj imm
#
# Formats
@@ -70,6 +72,8 @@
@fc .... ........ ..... ..... .. cj:3 fd:5 &fc
@cr .... ........ ..... ..... rj:5 .. cd:3 &cr
@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
+@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
+@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
#
# Fixed point arithmetic operation instruction
@@ -385,3 +389,23 @@ movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr
movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc
+
+#
+# Floating point load/store instruction
+#
+fld_s 0010 101100 ............ ..... ..... @fr_i12
+fst_s 0010 101101 ............ ..... ..... @fr_i12
+fld_d 0010 101110 ............ ..... ..... @fr_i12
+fst_d 0010 101111 ............ ..... ..... @fr_i12
+fldx_s 0011 10000011 00000 ..... ..... ..... @frr
+fldx_d 0011 10000011 01000 ..... ..... ..... @frr
+fstx_s 0011 10000011 10000 ..... ..... ..... @frr
+fstx_d 0011 10000011 11000 ..... ..... ..... @frr
+fldgt_s 0011 10000111 01000 ..... ..... ..... @frr
+fldgt_d 0011 10000111 01001 ..... ..... ..... @frr
+fldle_s 0011 10000111 01010 ..... ..... ..... @frr
+fldle_d 0011 10000111 01011 ..... ..... ..... @frr
+fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
+fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
+fstle_s 0011 10000111 01110 ..... ..... ..... @frr
+fstle_d 0011 10000111 01111 ..... ..... ..... @frr
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 26d60b50fd..daa77ade33 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -170,6 +170,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_fcmp.c.inc"
#include "insn_trans/trans_fcnv.c.inc"
#include "insn_trans/trans_fmov.c.inc"
+#include "insn_trans/trans_fmemory.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
new file mode 100644
index 0000000000..74ee98f63a
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static void maybe_nanbox_load(TCGv freg, MemOp mop)
+{
+ if ((mop & MO_SIZE) == MO_32) {
+ gen_nanbox_s(freg, freg);
+ }
+}
+
+static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
+{
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ maybe_nanbox_load(cpu_fpr[a->fd], mop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+
+ return true;
+}
+
+static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
+{
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+ return true;
+}
+
+static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ maybe_nanbox_load(cpu_fpr[a->fd], mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ maybe_nanbox_load(cpu_fpr[a->fd], mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ maybe_nanbox_load(cpu_fpr[a->fd], mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
+TRANS(fld_s, gen_fload_i, MO_TEUL)
+TRANS(fst_s, gen_fstore_i, MO_TEUL)
+TRANS(fld_d, gen_fload_i, MO_TEUQ)
+TRANS(fst_d, gen_fstore_i, MO_TEUQ)
+TRANS(fldx_s, gen_floadx, MO_TEUL)
+TRANS(fldx_d, gen_floadx, MO_TEUQ)
+TRANS(fstx_s, gen_fstorex, MO_TEUL)
+TRANS(fstx_d, gen_fstorex, MO_TEUQ)
+TRANS(fldgt_s, gen_fload_gt, MO_TEUL)
+TRANS(fldgt_d, gen_fload_gt, MO_TEUQ)
+TRANS(fldle_s, gen_fload_le, MO_TEUL)
+TRANS(fldle_d, gen_fload_le, MO_TEUQ)
+TRANS(fstgt_s, gen_fstore_gt, MO_TEUL)
+TRANS(fstgt_d, gen_fstore_gt, MO_TEUQ)
+TRANS(fstle_s, gen_fstore_le, MO_TEUL)
+TRANS(fstle_d, gen_fstore_le, MO_TEUQ)
--
2.34.1
next prev parent reply other threads:[~2022-06-06 23:30 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 23:14 [PULL 00/43] target/loongarch: Initial system support Richard Henderson
2022-06-06 23:14 ` [PULL 01/43] target/loongarch: Add README Richard Henderson
2022-06-06 23:14 ` [PULL 02/43] target/loongarch: Add core definition Richard Henderson
2022-06-06 23:14 ` [PULL 03/43] target/loongarch: Add main translation routines Richard Henderson
2022-06-06 23:14 ` [PULL 04/43] target/loongarch: Add fixed point arithmetic instruction translation Richard Henderson
2022-06-06 23:14 ` [PULL 05/43] target/loongarch: Add fixed point shift " Richard Henderson
2022-06-06 23:14 ` [PULL 06/43] target/loongarch: Add fixed point bit " Richard Henderson
2022-06-06 23:14 ` [PULL 07/43] target/loongarch: Add fixed point load/store " Richard Henderson
2022-06-06 23:14 ` [PULL 08/43] target/loongarch: Add fixed point atomic " Richard Henderson
2022-06-06 23:14 ` [PULL 09/43] target/loongarch: Add fixed point extra " Richard Henderson
2022-06-06 23:14 ` [PULL 10/43] target/loongarch: Add floating point arithmetic " Richard Henderson
2022-06-06 23:14 ` [PULL 11/43] target/loongarch: Add floating point comparison " Richard Henderson
2022-06-06 23:14 ` [PULL 12/43] target/loongarch: Add floating point conversion " Richard Henderson
2022-06-06 23:14 ` [PULL 13/43] target/loongarch: Add floating point move " Richard Henderson
2022-06-06 23:14 ` Richard Henderson [this message]
2022-06-06 23:14 ` [PULL 15/43] target/loongarch: Add branch " Richard Henderson
2022-06-06 23:14 ` [PULL 16/43] target/loongarch: Add disassembler Richard Henderson
2022-06-06 23:14 ` [PULL 17/43] target/loongarch: Add target build suport Richard Henderson
2022-06-06 23:14 ` [PULL 18/43] target/loongarch: Add system emulation introduction Richard Henderson
2022-06-06 23:14 ` [PULL 19/43] target/loongarch: Add CSRs definition Richard Henderson
2022-06-06 23:14 ` [PULL 20/43] target/loongarch: Add basic vmstate description of CPU Richard Henderson
2022-06-06 23:14 ` [PULL 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Richard Henderson
2022-06-06 23:14 ` [PULL 22/43] target/loongarch: Add MMU support for LoongArch CPU Richard Henderson
2022-06-06 23:14 ` [PULL 23/43] target/loongarch: Add LoongArch interrupt and exception handle Richard Henderson
2022-06-06 23:14 ` [PULL 24/43] target/loongarch: Add constant timer support Richard Henderson
2022-06-06 23:14 ` [PULL 25/43] target/loongarch: Add LoongArch CSR instruction Richard Henderson
2022-06-06 23:14 ` [PULL 26/43] target/loongarch: Add LoongArch IOCSR instruction Richard Henderson
2022-06-06 23:14 ` [PULL 27/43] target/loongarch: Add TLB instruction support Richard Henderson
2024-11-07 17:33 ` Peter Maydell
2024-11-26 13:13 ` Peter Maydell
2025-02-10 11:37 ` Peter Maydell
2022-06-06 23:14 ` [PULL 28/43] target/loongarch: Add other core instructions support Richard Henderson
2022-06-06 23:14 ` [PULL 29/43] target/loongarch: Add timer related " Richard Henderson
2022-06-06 23:14 ` [PULL 30/43] hw/loongarch: Add support loongson3 virt machine type Richard Henderson
2022-06-06 23:14 ` [PULL 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Richard Henderson
2022-06-06 23:14 ` [PULL 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Richard Henderson
2022-06-06 23:14 ` [PULL 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Richard Henderson
2022-06-06 23:14 ` [PULL 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Richard Henderson
2022-06-06 23:14 ` [PULL 35/43] hw/loongarch: Add irq hierarchy for the system Richard Henderson
2022-06-06 23:14 ` [PULL 36/43] Enable common virtio pci support for LoongArch Richard Henderson
2022-06-06 23:14 ` [PULL 37/43] hw/loongarch: Add some devices support for 3A5000 Richard Henderson
2022-06-06 23:14 ` [PULL 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Richard Henderson
2022-06-28 11:05 ` Peter Maydell
2022-06-28 12:04 ` yangxiaojuan
2022-06-06 23:14 ` [PULL 39/43] hw/loongarch: Add LoongArch load elf function Richard Henderson
2022-06-06 23:14 ` [PULL 40/43] hw/loongarch: Add LoongArch virt power manager support Richard Henderson
2022-06-06 23:14 ` [PULL 41/43] target/loongarch: Add gdb support Richard Henderson
2022-06-06 23:14 ` [PULL 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Richard Henderson
2022-06-06 23:14 ` [PULL 43/43] target/loongarch: 'make check-tcg' support Richard Henderson
2022-06-07 1:21 ` [PULL 00/43] target/loongarch: Initial system support Richard Henderson
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