* [PATCH v2] hw/cxl: Fix missing write mask for HDM decoder target list registers
@ 2022-06-07 10:56 Jonathan Cameron via
2022-06-07 11:06 ` Jonathan Cameron via
0 siblings, 1 reply; 3+ messages in thread
From: Jonathan Cameron via @ 2022-06-07 10:56 UTC (permalink / raw)
To: qemu-devel, Michael S . Tsirkin, Ben Widawsky
Cc: Paolo Bonzini, linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Shameerali Kolothum Thodi
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v2: (Ben Widawsky)
- Correctly set a tighter write mask for the endpoint devices where this
register has a different use.
hw/cxl/cxl-component-utils.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 7985c9bfca..40a0f752f2 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
}
-static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
+static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
+ enum reg_type type)
{
int decoder_count = 1;
int i;
@@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
+ if (type == CXL2_DEVICE) {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000;
+ } else {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
+ }
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
}
}
--
2.32.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] hw/cxl: Fix missing write mask for HDM decoder target list registers
2022-06-07 10:56 [PATCH v2] hw/cxl: Fix missing write mask for HDM decoder target list registers Jonathan Cameron via
@ 2022-06-07 11:06 ` Jonathan Cameron via
2022-06-07 15:57 ` Jonathan Cameron via
0 siblings, 1 reply; 3+ messages in thread
From: Jonathan Cameron via @ 2022-06-07 11:06 UTC (permalink / raw)
To: qemu-devel, Michael S . Tsirkin, Ben Widawsky
Cc: Paolo Bonzini, linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Shameerali Kolothum Thodi
On Tue, 7 Jun 2022 11:56:17 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> Without being able to write these registers, no interleaving is possible.
> More refined checks of HDM register state on commit to follow.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+Cc Ben on current address.
Which reminds me - Ben, when you have time please send an update
to MAINTAINERS to switch to your preferred email address going forwards.
Thanks,
Jonathan
> ---
> v2: (Ben Widawsky)
> - Correctly set a tighter write mask for the endpoint devices where this
> register has a different use.
>
> hw/cxl/cxl-component-utils.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index 7985c9bfca..40a0f752f2 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
> reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
> }
>
> -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
> + enum reg_type type)
> {
> int decoder_count = 1;
> int i;
> @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
> write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
> write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
> + if (type == CXL2_DEVICE) {
> + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000;
> + } else {
> + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
> + }
> + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
> }
> }
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] hw/cxl: Fix missing write mask for HDM decoder target list registers
2022-06-07 11:06 ` Jonathan Cameron via
@ 2022-06-07 15:57 ` Jonathan Cameron via
0 siblings, 0 replies; 3+ messages in thread
From: Jonathan Cameron via @ 2022-06-07 15:57 UTC (permalink / raw)
To: qemu-devel, Michael S . Tsirkin, Ben Widawsky
Cc: Paolo Bonzini, linux-cxl, linuxarm, alex.bennee, Marcel Apfelbaum,
Igor Mammedov, Markus Armbruster, Mark Cave-Ayland,
Adam Manzanares, Tong Zhang, Shameerali Kolothum Thodi
On Tue, 7 Jun 2022 12:06:12 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> On Tue, 7 Jun 2022 11:56:17 +0100
> Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
>
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> +Cc Ben on current address.
>
> Which reminds me - Ben, when you have time please send an update
> to MAINTAINERS to switch to your preferred email address going forwards.
Ignore this version as clearly broken due to some git command line
fumbling. v3 shortly.
>
> Thanks,
>
> Jonathan
>
> > ---
> > v2: (Ben Widawsky)
> > - Correctly set a tighter write mask for the endpoint devices where this
> > register has a different use.
> >
> > hw/cxl/cxl-component-utils.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > index 7985c9bfca..40a0f752f2 100644
> > --- a/hw/cxl/cxl-component-utils.c
> > +++ b/hw/cxl/cxl-component-utils.c
> > @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
> > reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
> > }
> >
> > -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> > +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
> > + enum reg_type type)
> > {
> > int decoder_count = 1;
> > int i;
> > @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
> > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
> > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
> > + if (type == CXL2_DEVICE) {
> > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000;
> > + } else {
> > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
> > + }
> > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
> > }
> > }
> >
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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