From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE91FC433EF for ; Tue, 7 Jun 2022 12:18:57 +0000 (UTC) Received: from localhost ([::1]:37492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyYAi-0003iC-L6 for qemu-devel@archiver.kernel.org; Tue, 07 Jun 2022 08:18:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyX2S-0000z7-Et for qemu-devel@nongnu.org; Tue, 07 Jun 2022 07:06:20 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyX2P-0006Yg-UD for qemu-devel@nongnu.org; Tue, 07 Jun 2022 07:06:19 -0400 Received: from fraeml703-chm.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4LHS8r4HPcz684Xd; Tue, 7 Jun 2022 19:01:32 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml703-chm.china.huawei.com (10.206.15.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Tue, 7 Jun 2022 13:06:14 +0200 Received: from localhost (10.202.226.42) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 7 Jun 2022 12:06:13 +0100 Date: Tue, 7 Jun 2022 12:06:12 +0100 To: , "Michael S . Tsirkin" , "Ben Widawsky" CC: Paolo Bonzini , , , , Marcel Apfelbaum , Igor Mammedov , Markus Armbruster , Mark Cave-Ayland , "Adam Manzanares" , Tong Zhang , Shameerali Kolothum Thodi Subject: Re: [PATCH v2] hw/cxl: Fix missing write mask for HDM decoder target list registers Message-ID: <20220607120612.00000db7@Huawei.com> In-Reply-To: <20220607105617.16459-1-Jonathan.Cameron@huawei.com> References: <20220607105617.16459-1-Jonathan.Cameron@huawei.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.29; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.42] X-ClientProxiedBy: lhreml732-chm.china.huawei.com (10.201.108.83) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via On Tue, 7 Jun 2022 11:56:17 +0100 Jonathan Cameron wrote: > Without being able to write these registers, no interleaving is possible. > More refined checks of HDM register state on commit to follow. > > Signed-off-by: Jonathan Cameron +Cc Ben on current address. Which reminds me - Ben, when you have time please send an update to MAINTAINERS to switch to your preferred email address going forwards. Thanks, Jonathan > --- > v2: (Ben Widawsky) > - Correctly set a tighter write mask for the endpoint devices where this > register has a different use. > > hw/cxl/cxl-component-utils.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 7985c9bfca..40a0f752f2 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk) > reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00; > } > > -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > + enum reg_type type) > { > int decoder_count = 1; > int i; > @@ -174,6 +175,12 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) > write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000; > write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff; > write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff; > + if (type == CXL2_DEVICE) { > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xf0000000; > + } else { > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff; > + } > + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff; > } > } >