From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v2 47/71] target/arm: Export unpredicated ld/st from translate-sve.c
Date: Tue, 7 Jun 2022 13:32:42 -0700 [thread overview]
Message-ID: <20220607203306.657998-48-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org>
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 3 +++
target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++----------
2 files changed, 39 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index c341c95582..54503745a9 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -165,4 +165,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, int64_t shift,
uint32_t opr_sz, uint32_t max_sz);
+void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+
#endif /* TARGET_ARM_TRANSLATE_A64_H */
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 13bdd027a5..adf0cd3e68 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4294,7 +4294,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
* The load should begin at the address Rn + IMM.
*/
-static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
+ int len, int rn, int imm)
{
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
@@ -4320,7 +4321,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
t0 = tcg_temp_new_i64();
for (i = 0; i < len_align; i += 8) {
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ);
- tcg_gen_st_i64(t0, cpu_env, vofs + i);
+ tcg_gen_st_i64(t0, base, vofs + i);
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
tcg_temp_free_i64(t0);
@@ -4333,6 +4334,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);
+ if (base != cpu_env) {
+ TCGv_ptr b = tcg_temp_local_new_ptr();
+ tcg_gen_mov_ptr(b, base);
+ base = b;
+ }
+
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -4340,7 +4347,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
tp = tcg_temp_new_ptr();
- tcg_gen_add_ptr(tp, cpu_env, i);
+ tcg_gen_add_ptr(tp, base, i);
tcg_gen_addi_ptr(i, i, 8);
tcg_gen_st_i64(t0, tp, vofs);
tcg_temp_free_ptr(tp);
@@ -4348,6 +4355,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);
+
+ if (base != cpu_env) {
+ tcg_temp_free_ptr(base);
+ assert(len_remain == 0);
+ }
}
/*
@@ -4376,13 +4388,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
default:
g_assert_not_reached();
}
- tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
+ tcg_gen_st_i64(t0, base, vofs + len_align);
tcg_temp_free_i64(t0);
}
}
/* Similarly for stores. */
-static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
+ int len, int rn, int imm)
{
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
@@ -4408,7 +4421,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
t0 = tcg_temp_new_i64();
for (i = 0; i < len_align; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, vofs + i);
+ tcg_gen_ld_i64(t0, base, vofs + i);
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ);
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
@@ -4422,11 +4435,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);
+ if (base != cpu_env) {
+ TCGv_ptr b = tcg_temp_local_new_ptr();
+ tcg_gen_mov_ptr(b, base);
+ base = b;
+ }
+
gen_set_label(loop);
t0 = tcg_temp_new_i64();
tp = tcg_temp_new_ptr();
- tcg_gen_add_ptr(tp, cpu_env, i);
+ tcg_gen_add_ptr(tp, base, i);
tcg_gen_ld_i64(t0, tp, vofs);
tcg_gen_addi_ptr(i, i, 8);
tcg_temp_free_ptr(tp);
@@ -4437,12 +4456,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);
+
+ if (base != cpu_env) {
+ tcg_temp_free_ptr(base);
+ assert(len_remain == 0);
+ }
}
/* Predicate register stores can be any multiple of 2. */
if (len_remain) {
t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
+ tcg_gen_ld_i64(t0, base, vofs + len_align);
switch (len_remain) {
case 2:
@@ -4474,7 +4498,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- do_ldr(s, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4487,7 +4511,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- do_ldr(s, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4500,7 +4524,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- do_str(s, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4513,7 +4537,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- do_str(s, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
--
2.34.1
next prev parent reply other threads:[~2022-06-07 21:17 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-07 20:31 [PATCH v2 00/71] target/arm: Scalable Matrix Extension Richard Henderson
2022-06-07 20:31 ` [PATCH v2 01/71] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL Richard Henderson
2022-06-07 20:31 ` [PATCH v2 02/71] linux-user/aarch64: Introduce sve_vq Richard Henderson
2022-06-07 20:31 ` [PATCH v2 03/71] target/arm: Remove route_to_el2 check from sve_exception_el Richard Henderson
2022-06-07 20:31 ` [PATCH v2 04/71] target/arm: Remove fp checks " Richard Henderson
2022-06-07 20:32 ` [PATCH v2 05/71] target/arm: Add el_is_in_host Richard Henderson
2022-06-07 20:32 ` [PATCH v2 06/71] target/arm: Use el_is_in_host for sve_zcr_len_for_el Richard Henderson
2022-06-07 20:32 ` [PATCH v2 07/71] target/arm: Use el_is_in_host for sve_exception_el Richard Henderson
2022-06-07 20:32 ` [PATCH v2 08/71] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el Richard Henderson
2022-06-07 20:32 ` [PATCH v2 09/71] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Richard Henderson
2022-06-07 20:32 ` [PATCH v2 10/71] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Richard Henderson
2022-06-07 20:32 ` [PATCH v2 11/71] target/arm: Use uint32_t instead of bitmap for sve vq's Richard Henderson
2022-06-07 20:32 ` [PATCH v2 12/71] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Richard Henderson
2022-06-07 20:32 ` [PATCH v2 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h Richard Henderson
2022-06-07 20:32 ` [PATCH v2 14/71] target/arm: Export sve contiguous ldst support functions Richard Henderson
2022-06-07 20:32 ` [PATCH v2 15/71] target/arm: Move expand_pred_b to vec_internal.h Richard Henderson
2022-06-07 20:32 ` [PATCH v2 16/71] target/arm: Use expand_pred_b in mve_helper.c Richard Henderson
2022-06-07 20:32 ` [PATCH v2 17/71] target/arm: Move expand_pred_h to vec_internal.h Richard Henderson
2022-06-07 20:32 ` [PATCH v2 18/71] target/arm: Export bfdotadd from vec_helper.c Richard Henderson
2022-06-07 20:32 ` [PATCH v2 19/71] target/arm: Add isar_feature_aa64_sme Richard Henderson
2022-06-07 20:32 ` [PATCH v2 20/71] target/arm: Add ID_AA64SMFR0_EL1 Richard Henderson
2022-06-07 20:32 ` [PATCH v2 21/71] target/arm: Implement TPIDR2_EL0 Richard Henderson
2022-06-09 15:24 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 22/71] target/arm: Add SMEEXC_EL to TB flags Richard Henderson
2022-06-07 20:32 ` [PATCH v2 23/71] target/arm: Add syn_smetrap Richard Henderson
2022-06-07 20:32 ` [PATCH v2 24/71] target/arm: Add ARM_CP_SME Richard Henderson
2022-06-07 20:32 ` [PATCH v2 25/71] target/arm: Add SVCR Richard Henderson
2022-06-09 15:25 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 26/71] target/arm: Add SMCR_ELx Richard Henderson
2022-06-07 20:32 ` [PATCH v2 27/71] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2 Richard Henderson
2022-06-07 20:32 ` [PATCH v2 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags Richard Henderson
2022-06-07 20:32 ` [PATCH v2 29/71] target/arm: Add the SME ZA storage to CPUARMState Richard Henderson
2022-06-10 12:59 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 30/71] target/arm: Implement SMSTART, SMSTOP Richard Henderson
2022-06-07 20:32 ` [PATCH v2 31/71] target/arm: Move error for sve%d property to arm_cpu_sve_finalize Richard Henderson
2022-06-09 15:29 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 32/71] target/arm: Create ARMVQMap Richard Henderson
2022-06-09 15:30 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 33/71] target/arm: Generalize cpu_arm_{get,set}_vq Richard Henderson
2022-06-09 15:30 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len Richard Henderson
2022-06-09 15:31 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 35/71] target/arm: Move arm_cpu_*_finalize to internals.h Richard Henderson
2022-06-09 15:31 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 36/71] target/arm: Unexport aarch64_add_*_properties Richard Henderson
2022-06-09 15:32 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 37/71] target/arm: Add cpu properties for SME Richard Henderson
2022-06-09 15:32 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 38/71] target/arm: Introduce sve_vqm1_for_el_sm Richard Henderson
2022-06-09 15:33 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 39/71] target/arm: Add SVL to TB flags Richard Henderson
2022-06-09 15:33 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h Richard Henderson
2022-06-09 15:34 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme Richard Henderson
2022-06-09 15:35 ` Peter Maydell
2022-06-09 22:58 ` Richard Henderson
2022-06-10 9:02 ` Peter Maydell
2022-06-07 20:32 ` [PATCH v2 42/71] target/arm: Trap AdvSIMD usage when Streaming SVE is active Richard Henderson
2022-06-07 20:32 ` [PATCH v2 43/71] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Richard Henderson
2022-06-07 20:32 ` [PATCH v2 44/71] target/arm: Implement SME ZERO Richard Henderson
2022-06-07 20:32 ` [PATCH v2 45/71] target/arm: Implement SME MOVA Richard Henderson
2022-06-07 20:32 ` [PATCH v2 46/71] target/arm: Implement SME LD1, ST1 Richard Henderson
2022-06-07 20:32 ` Richard Henderson [this message]
2022-06-07 20:32 ` [PATCH v2 48/71] target/arm: Implement SME LDR, STR Richard Henderson
2022-06-07 20:32 ` [PATCH v2 49/71] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
2022-06-07 20:32 ` [PATCH v2 50/71] target/arm: Implement FMOPA, FMOPS (non-widening) Richard Henderson
2022-06-07 20:32 ` [PATCH v2 51/71] target/arm: Implement BFMOPA, BFMOPS Richard Henderson
2022-06-07 20:32 ` [PATCH v2 52/71] target/arm: Implement FMOPA, FMOPS (widening) Richard Henderson
2022-06-07 20:32 ` [PATCH v2 53/71] target/arm: Implement SME integer outer product Richard Henderson
2022-06-07 20:32 ` [PATCH v2 54/71] target/arm: Implement PSEL Richard Henderson
2022-06-07 20:32 ` [PATCH v2 55/71] target/arm: Implement REVD Richard Henderson
2022-06-07 20:32 ` [PATCH v2 56/71] target/arm: Implement SCLAMP, UCLAMP Richard Henderson
2022-06-07 20:32 ` [PATCH v2 57/71] target/arm: Reset streaming sve state on exception boundaries Richard Henderson
2022-06-07 20:32 ` [PATCH v2 58/71] target/arm: Enable SME for -cpu max Richard Henderson
2022-06-07 20:32 ` [PATCH v2 59/71] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
2022-06-07 20:32 ` [PATCH v2 60/71] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
2022-06-07 20:32 ` [PATCH v2 61/71] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
2022-06-07 20:32 ` [PATCH v2 62/71] linux-user/aarch64: Tidy target_restore_sigframe error return Richard Henderson
2022-06-07 20:32 ` [PATCH v2 63/71] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
2022-06-07 20:32 ` [PATCH v2 64/71] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
2022-06-07 20:33 ` [PATCH v2 65/71] linux-user/aarch64: Move sve record checks into restore Richard Henderson
2022-06-07 20:33 ` [PATCH v2 66/71] linux-user/aarch64: Implement SME signal handling Richard Henderson
2022-06-07 20:33 ` [PATCH v2 67/71] linux-user: Rename sve prctls Richard Henderson
2022-06-07 20:33 ` [PATCH v2 68/71] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Richard Henderson
2022-06-07 20:33 ` [PATCH v2 69/71] target/arm: Only set ZEN in reset if SVE present Richard Henderson
2022-06-07 20:33 ` [PATCH v2 70/71] target/arm: Enable SME for user-only Richard Henderson
2022-06-07 20:33 ` [PATCH v2 71/71] linux-user/aarch64: Add SME related hwcap entries Richard Henderson
2022-06-09 15:22 ` [PATCH v2 00/71] target/arm: Scalable Matrix Extension Peter Maydell
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