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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Paolo Bonzini <pbonzini@redhat.com>, <qemu-devel@nongnu.org>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Ben Widawsky <bwidawsk@kernel.org>
Cc: <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>,
	<alex.bennee@linaro.org>, Marcel Apfelbaum <marcel@redhat.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Markus Armbruster <armbru@redhat.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	Adam Manzanares <a.manzanares@samsung.com>,
	Tong Zhang <ztong0001@gmail.com>,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>
Subject: [PATCH v3 2/8] hw/acpi/cxl: Pass in the CXLState directly rather than MachineState
Date: Wed, 8 Jun 2022 15:54:34 +0100	[thread overview]
Message-ID: <20220608145440.26106-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220608145440.26106-1-Jonathan.Cameron@huawei.com>

Refactoring step on path to moving all CXL state out of
MachineState.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
 hw/acpi/cxl.c         | 9 ++++-----
 hw/i386/acpi-build.c  | 4 ++--
 include/hw/acpi/cxl.h | 5 +++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 31d5235136..2bf8c07993 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -65,9 +65,8 @@ static void cedt_build_chbs(GArray *table_data, PXBDev *cxl)
  * Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory
  * interleaving.
  */
-static void cedt_build_cfmws(GArray *table_data, MachineState *ms)
+static void cedt_build_cfmws(GArray *table_data, CXLState *cxls)
 {
-    CXLState *cxls = ms->cxl_devices_state;
     GList *it;
 
     for (it = cxls->fixed_windows; it; it = it->next) {
@@ -129,9 +128,9 @@ static int cxl_foreach_pxb_hb(Object *obj, void *opaque)
     return 0;
 }
 
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
                     BIOSLinker *linker, const char *oem_id,
-                    const char *oem_table_id)
+                    const char *oem_table_id, CXLState *cxl_state)
 {
     Aml *cedt;
     AcpiTable table = { .sig = "CEDT", .rev = 1, .oem_id = oem_id,
@@ -144,7 +143,7 @@ void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
     /* reserve space for CEDT header */
 
     object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt);
-    cedt_build_cfmws(cedt->buf, ms);
+    cedt_build_cfmws(cedt->buf, cxl_state);
 
     /* copy AML table into ACPI tables blob and patch header there */
     g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c125939ed6..2e3b1dd9a2 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2712,8 +2712,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
                           x86ms->oem_id, x86ms->oem_table_id);
     }
     if (machine->cxl_devices_state->is_enabled) {
-        cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker,
-                       x86ms->oem_id, x86ms->oem_table_id);
+        cxl_build_cedt(table_offsets, tables_blob, tables->linker,
+                       x86ms->oem_id, x86ms->oem_table_id, machine->cxl_devices_state);
     }
 
     acpi_add_table(table_offsets, tables_blob);
diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h
index 0c496538c0..acf4418886 100644
--- a/include/hw/acpi/cxl.h
+++ b/include/hw/acpi/cxl.h
@@ -19,10 +19,11 @@
 #define HW_ACPI_CXL_H
 
 #include "hw/acpi/bios-linker-loader.h"
+#include "hw/cxl/cxl.h"
 
-void cxl_build_cedt(MachineState *ms, GArray *table_offsets, GArray *table_data,
+void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
                     BIOSLinker *linker, const char *oem_id,
-                    const char *oem_table_id);
+                    const char *oem_table_id, CXLState *cxl_state);
 void build_cxl_osc_method(Aml *dev);
 
 #endif
-- 
2.32.0



  parent reply	other threads:[~2022-06-08 15:03 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-08 14:54 [PATCH v3 0/8] hw/cxl: Move CXL emulation options and state to machines Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter Jonathan Cameron via
2022-06-08 14:54 ` Jonathan Cameron via [this message]
2022-06-08 14:54 ` [PATCH v3 3/8] hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.c Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 4/8] tests/acpi: Allow modification of q35 CXL CEDT table Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 6/8] tests/acpi: Update q35/CEDT.cxl for new memory addresses Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 7/8] hw/cxl: Move the CXLState from MachineState to machine type specific state Jonathan Cameron via
2022-06-08 14:54 ` [PATCH v3 8/8] hw/machine: Drop cxl_supported flag as no longer useful Jonathan Cameron via

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