From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 48/55] target/arm: Split out load/store primitives to sve_ldst_internal.h
Date: Thu, 9 Jun 2022 10:05:30 +0100 [thread overview]
Message-ID: <20220609090537.1971756-49-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Begin creation of sve_ldst_internal.h by moving the primitives
that access host and tlb memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve_ldst_internal.h | 127 +++++++++++++++++++++++++++++++++
target/arm/sve_helper.c | 107 +--------------------------
2 files changed, 128 insertions(+), 106 deletions(-)
create mode 100644 target/arm/sve_ldst_internal.h
diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h
new file mode 100644
index 00000000000..ef9117e84c1
--- /dev/null
+++ b/target/arm/sve_ldst_internal.h
@@ -0,0 +1,127 @@
+/*
+ * ARM SVE Load/Store Helpers
+ *
+ * Copyright (c) 2018-2022 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARM_SVE_LDST_INTERNAL_H
+#define TARGET_ARM_SVE_LDST_INTERNAL_H
+
+#include "exec/cpu_ldst.h"
+
+/*
+ * Load one element into @vd + @reg_off from @host.
+ * The controlling predicate is known to be true.
+ */
+typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
+
+/*
+ * Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
+ * The controlling predicate is known to be true.
+ */
+typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
+ target_ulong vaddr, uintptr_t retaddr);
+
+/*
+ * Generate the above primitives.
+ */
+
+#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
+static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
+{ TYPEM val = HOST(host); *(TYPEE *)(vd + H(reg_off)) = val; }
+
+#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
+static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
+{ TYPEM val = *(TYPEE *)(vd + H(reg_off)); HOST(host, val); }
+
+#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
+static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \
+ intptr_t reg_off, target_ulong addr, uintptr_t ra) \
+{ \
+ TYPEM val = TLB(env, useronly_clean_ptr(addr), ra); \
+ *(TYPEE *)(vd + H(reg_off)) = val; \
+}
+
+#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
+static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \
+ intptr_t reg_off, target_ulong addr, uintptr_t ra) \
+{ \
+ TYPEM val = *(TYPEE *)(vd + H(reg_off)); \
+ TLB(env, useronly_clean_ptr(addr), val, ra); \
+}
+
+#define DO_LD_PRIM_1(NAME, H, TE, TM) \
+ DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
+ DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
+
+DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
+DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
+DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t)
+DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t)
+DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
+DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t)
+DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t)
+
+#define DO_ST_PRIM_1(NAME, H, TE, TM) \
+ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
+ DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
+
+DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
+DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
+DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
+DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t)
+
+#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
+ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
+ DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
+ DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
+ DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
+
+#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
+ DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
+ DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
+ DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
+ DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
+
+DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
+DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
+DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
+DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw)
+DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw)
+
+DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
+DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
+DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw)
+
+DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
+DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl)
+DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl)
+
+DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
+DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl)
+
+DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq)
+DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq)
+
+#undef DO_LD_TLB
+#undef DO_ST_TLB
+#undef DO_LD_HOST
+#undef DO_LD_PRIM_1
+#undef DO_ST_PRIM_1
+#undef DO_LD_PRIM_2
+#undef DO_ST_PRIM_2
+
+#endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 3bdcd4ce9d0..0c6dde00aa6 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -21,12 +21,12 @@
#include "cpu.h"
#include "internals.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h"
#include "tcg/tcg.h"
#include "vec_internal.h"
+#include "sve_ldst_internal.h"
/* Return a value for NZCV as per the ARM PredTest pseudofunction.
@@ -5301,111 +5301,6 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
* Load contiguous data, protected by a governing predicate.
*/
-/*
- * Load one element into @vd + @reg_off from @host.
- * The controlling predicate is known to be true.
- */
-typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host);
-
-/*
- * Load one element into @vd + @reg_off from (@env, @vaddr, @ra).
- * The controlling predicate is known to be true.
- */
-typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off,
- target_ulong vaddr, uintptr_t retaddr);
-
-/*
- * Generate the above primitives.
- */
-
-#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \
-static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
-{ \
- TYPEM val = HOST(host); \
- *(TYPEE *)(vd + H(reg_off)) = val; \
-}
-
-#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \
-static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \
-{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); }
-
-#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
- target_ulong addr, uintptr_t ra) \
-{ \
- *(TYPEE *)(vd + H(reg_off)) = \
- (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); \
-}
-
-#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \
-static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \
- target_ulong addr, uintptr_t ra) \
-{ \
- TLB(env, useronly_clean_ptr(addr), \
- (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \
-}
-
-#define DO_LD_PRIM_1(NAME, H, TE, TM) \
- DO_LD_HOST(NAME, H, TE, TM, ldub_p) \
- DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra)
-
-DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t)
-DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t)
-DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t)
-DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t)
-DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t)
-DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t)
-DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t)
-
-#define DO_ST_PRIM_1(NAME, H, TE, TM) \
- DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \
- DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra)
-
-DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t)
-DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t)
-DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t)
-DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t)
-
-#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \
- DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \
- DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \
- DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \
- DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra)
-
-#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \
- DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
- DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
- DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
- DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
-
-DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw)
-DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw)
-DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw)
-DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw)
-DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw)
-
-DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw)
-DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw)
-DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw)
-
-DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl)
-DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl)
-DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl)
-
-DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl)
-DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl)
-
-DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq)
-DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq)
-
-#undef DO_LD_TLB
-#undef DO_ST_TLB
-#undef DO_LD_HOST
-#undef DO_LD_PRIM_1
-#undef DO_ST_PRIM_1
-#undef DO_LD_PRIM_2
-#undef DO_ST_PRIM_2
-
/*
* Skip through a sequence of inactive elements in the guarding predicate @vg,
* beginning at @reg_off bounded by @reg_max. Return the offset of the active
--
2.25.1
next prev parent reply other threads:[~2022-06-09 10:22 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 9:04 [PULL 00/55] target-arm queue Peter Maydell
2022-06-09 9:04 ` [PULL 01/55] target/arm: Declare support for FEAT_RASv1p1 Peter Maydell
2022-06-09 9:04 ` [PULL 02/55] target/arm: Implement FEAT_DoubleFault Peter Maydell
2022-06-09 9:04 ` [PULL 03/55] Fix 'writeable' typos Peter Maydell
2022-06-09 9:04 ` [PULL 04/55] xlnx_dp: fix the wrong register size Peter Maydell
2022-06-09 9:04 ` [PULL 05/55] xlnx_dp: Introduce a vblank signal Peter Maydell
2022-06-09 9:04 ` [PULL 06/55] xlnx_dp: Fix the interrupt disable logic Peter Maydell
2022-06-09 9:04 ` [PULL 07/55] xlnx-zynqmp: fix the irq mapping for the display port and its dma Peter Maydell
2022-06-09 9:04 ` [PULL 08/55] target/arm: Move stage_1_mmu_idx decl to internals.h Peter Maydell
2022-06-09 9:04 ` [PULL 09/55] target/arm: Move get_phys_addr to ptw.c Peter Maydell
2022-06-09 9:04 ` [PULL 10/55] target/arm: Move get_phys_addr_v5 " Peter Maydell
2022-06-09 9:04 ` [PULL 11/55] target/arm: Move get_phys_addr_v6 " Peter Maydell
2022-06-09 9:04 ` [PULL 12/55] target/arm: Move get_phys_addr_pmsav5 " Peter Maydell
2022-06-09 9:04 ` [PULL 13/55] target/arm: Move get_phys_addr_pmsav7_default " Peter Maydell
2022-06-09 9:04 ` [PULL 14/55] target/arm: Move get_phys_addr_pmsav7 " Peter Maydell
2022-06-09 9:04 ` [PULL 15/55] target/arm: Move get_phys_addr_pmsav8 " Peter Maydell
2022-06-09 9:04 ` [PULL 16/55] target/arm: Move pmsav8_mpu_lookup " Peter Maydell
2022-06-09 9:04 ` [PULL 17/55] target/arm: Move pmsav7_use_background_region " Peter Maydell
2022-06-09 9:05 ` [PULL 18/55] target/arm: Move v8m_security_lookup " Peter Maydell
2022-06-09 9:05 ` [PULL 19/55] target/arm: Move m_is_{ppb,system}_region " Peter Maydell
2022-06-09 9:05 ` [PULL 20/55] target/arm: Move get_level1_table_address " Peter Maydell
2022-06-09 9:05 ` [PULL 21/55] target/arm: Move combine_cacheattrs and subroutines " Peter Maydell
2022-06-09 9:05 ` [PULL 22/55] target/arm: Move get_phys_addr_lpae " Peter Maydell
2022-06-09 9:05 ` [PULL 23/55] target/arm: Move arm_{ldl,ldq}_ptw " Peter Maydell
2022-06-09 9:05 ` [PULL 24/55] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c Peter Maydell
2022-06-09 9:05 ` [PULL 25/55] target/arm: Move arm_pamax, pamax_map into ptw.c Peter Maydell
2022-06-09 9:05 ` [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c Peter Maydell
2022-06-09 9:05 ` [PULL 27/55] target/arm: Move check_s2_mmu_setup " Peter Maydell
2022-06-09 9:05 ` [PULL 28/55] target/arm: Move aa32_va_parameters " Peter Maydell
2022-06-09 9:05 ` [PULL 29/55] target/arm: Move ap_to_tw_prot etc " Peter Maydell
2022-06-09 9:05 ` [PULL 30/55] target/arm: Move regime_is_user " Peter Maydell
2022-06-09 9:05 ` [PULL 31/55] target/arm: Move regime_ttbr " Peter Maydell
2022-06-09 9:05 ` [PULL 32/55] target/arm: Move regime_translation_disabled " Peter Maydell
2022-06-09 9:05 ` [PULL 33/55] target/arm: Move arm_cpu_get_phys_page_attrs_debug " Peter Maydell
2022-06-09 9:05 ` [PULL 34/55] target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx " Peter Maydell
2022-06-09 9:05 ` [PULL 35/55] target/arm: Pass CPUARMState to arm_ld[lq]_ptw Peter Maydell
2022-06-09 9:05 ` [PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL Peter Maydell
2022-06-09 9:05 ` [PULL 37/55] linux-user/aarch64: Introduce sve_vq Peter Maydell
2022-06-09 9:05 ` [PULL 38/55] target/arm: Remove route_to_el2 check from sve_exception_el Peter Maydell
2022-06-09 9:05 ` [PULL 39/55] target/arm: Remove fp checks " Peter Maydell
2022-06-09 9:05 ` [PULL 40/55] target/arm: Add el_is_in_host Peter Maydell
2022-06-09 9:05 ` [PULL 41/55] target/arm: Use el_is_in_host for sve_zcr_len_for_el Peter Maydell
2022-06-09 9:05 ` [PULL 42/55] target/arm: Use el_is_in_host for sve_exception_el Peter Maydell
2022-06-09 9:05 ` [PULL 43/55] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el Peter Maydell
2022-06-09 9:05 ` [PULL 44/55] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Peter Maydell
2022-06-09 9:05 ` [PULL 45/55] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Peter Maydell
2022-06-09 9:05 ` [PULL 46/55] target/arm: Use uint32_t instead of bitmap for sve vq's Peter Maydell
2022-06-09 9:05 ` [PULL 47/55] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Peter Maydell
2022-06-09 9:05 ` Peter Maydell [this message]
2022-06-09 9:05 ` [PULL 49/55] target/arm: Export sve contiguous ldst support functions Peter Maydell
2022-06-09 9:05 ` [PULL 50/55] target/arm: Move expand_pred_b to vec_internal.h Peter Maydell
2022-06-09 9:05 ` [PULL 51/55] target/arm: Use expand_pred_b in mve_helper.c Peter Maydell
2022-06-09 9:05 ` [PULL 52/55] target/arm: Move expand_pred_h to vec_internal.h Peter Maydell
2022-06-09 9:05 ` [PULL 53/55] target/arm: Export bfdotadd from vec_helper.c Peter Maydell
2022-06-09 9:05 ` [PULL 54/55] target/arm: Add isar_feature_aa64_sme Peter Maydell
2022-06-09 9:05 ` [PULL 55/55] target/arm: Add ID_AA64SMFR0_EL1 Peter Maydell
2022-06-09 15:24 ` [PULL 00/55] target-arm queue Richard Henderson
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