From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <alex.bennee@linaro.org>,
Peter Maydell <peter.maydell@linaro.org>, <qemu-arm@nongnu.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
Ben Widawsky <bwidawsk@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, <linux-cxl@vger.kernel.org>,
<linuxarm@huawei.com>, Marcel Apfelbaum <marcel@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
Adam Manzanares <a.manzanares@samsung.com>,
Tong Zhang <ztong0001@gmail.com>,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>
Subject: [PATCH v11 0/2] arm/virt: CXL support via pxb_cxl
Date: Thu, 16 Jun 2022 15:19:48 +0100 [thread overview]
Message-ID: <20220616141950.23374-1-Jonathan.Cameron@huawei.com> (raw)
Previously patches 40 and 41 of
[PATCH v10 00/45] CXl 2.0 emulation Support
https://lore.kernel.org/qemu-devel/20220429144110.25167-45-Jonathan.Cameron@huawei.com/#r
Now the base CXL support including for x86/pc is upstream (patches 1-39)
there are no dependencies between the next few CXL elements in my queue
so they can be reviewed / merged in parallel. Hence I'll be sending switch
support (43-45) separately and hopefully DOE / CDAT support in a few days.
I'm assuming this particular series should go through the arm tree if
the maintainers are happy?
Changes since v10:
- CXL machine setup is now entirely from the supporting machines rather
than via code in machine.c and vl.c. Change made for x86 in:
https://lore.kernel.org/qemu-devel/20220608145440.26106-1-Jonathan.Cameron@huawei.com/
- Dropped Ben's sign off from patch 1 which resulted from him carrying
these patches of mine for a while. It isn't a useful bit of history
to carry now they are back to me.
This short series adds support for CXL host bridges and CXL fixed memory
windows on arm/virt. Two types of memory region are needed:
1. Register space for CXL host bridges (static allowance for 16)
2. CXL fixed memory windows: Ranges of host PA space which
are statically mapped to an interleave across 1 or more CXL host
bridges.
Both of these types of region are described via appropriate ACPI tables.
As the CEDT table is created with the same code as for x86 I don't think
there is much value in duplicating the existing CXL bios-tables test.
The second patch adds a single complex test. We test a lot more configurations
on x86 but it does not seem useful to duplicate them all on ARM and this single
test should act as a smoke test for any problems that occur.
Run through CI at:
https://gitlab.com/jic23/qemu/-/pipelines/564934276
Intermittent (unrelated I assume) failure in msys64 aio-test resolved
with a retry.
Thanks,
Jonathan
Jonathan Cameron (2):
hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances
pxb-cxl
qtest/cxl: Add aarch64 virt test for CXL
hw/arm/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++
hw/arm/virt.c | 44 ++++++++++++++++++++++++++++++++++++
include/hw/arm/virt.h | 3 +++
tests/qtest/cxl-test.c | 48 ++++++++++++++++++++++++++++++++--------
tests/qtest/meson.build | 1 +
5 files changed, 121 insertions(+), 9 deletions(-)
--
2.32.0
next reply other threads:[~2022-06-16 14:21 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-16 14:19 Jonathan Cameron via [this message]
2022-06-16 14:19 ` [PATCH v11 1/2] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron via
2022-06-24 10:48 ` Peter Maydell
2022-06-24 12:39 ` Jonathan Cameron via
2022-06-24 12:56 ` Peter Maydell
2022-06-24 14:08 ` Jonathan Cameron via
2022-06-24 14:54 ` Jonathan Cameron via
2022-06-24 15:01 ` Peter Maydell
2022-06-24 15:59 ` Jonathan Cameron via
2022-06-16 14:19 ` [PATCH v11 2/2] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron via
2022-06-24 10:41 ` Peter Maydell
2022-06-24 16:12 ` Peter Maydell
2022-06-24 17:59 ` Jonathan Cameron via
2022-06-24 9:07 ` [PATCH v11 0/2] arm/virt: CXL support via pxb_cxl Jonathan Cameron via
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