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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id v5-20020a1cf705000000b0039c5fb1f592sm5491396wmh.14.2022.06.16.06.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jun 2022 06:05:41 -0700 (PDT) Date: Thu, 16 Jun 2022 15:05:40 +0200 From: Igor Mammedov To: Joao Martins Cc: qemu-devel@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Daniel Jordan , David Edmondson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , Suravee Suthikulpanit Subject: Re: [PATCH v5 1/5] hw/i386: add 4g boundary start to X86MachineState Message-ID: <20220616150540.31b51edf@redhat.com> In-Reply-To: <20220520104532.9816-2-joao.m.martins@oracle.com> References: <20220520104532.9816-1-joao.m.martins@oracle.com> <20220520104532.9816-2-joao.m.martins@oracle.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 20 May 2022 11:45:28 +0100 Joao Martins wrote: > Rather than hardcoding the 4G boundary everywhere, introduce a > X86MachineState property @above_4g_mem_start and use it so far it's just field not a property /fix commit message/ > accordingly. > > This is in preparation for relocating ram-above-4g to be > dynamically start at 1T on AMD platforms. possibly needs to be rebased on top of current master to include cxl_base with comments fixed Reviewed-by: Igor Mammedov > > Signed-off-by: Joao Martins > --- > hw/i386/acpi-build.c | 2 +- > hw/i386/pc.c | 9 +++++---- > hw/i386/sgx.c | 2 +- > hw/i386/x86.c | 1 + > include/hw/i386/x86.h | 3 +++ > 5 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index c125939ed6f9..3160b20c9574 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -2120,7 +2120,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) > build_srat_memory(table_data, mem_base, mem_len, i - 1, > MEM_AFFINITY_ENABLED); > } > - mem_base = 1ULL << 32; > + mem_base = x86ms->above_4g_mem_start; > mem_len = next_base - x86ms->below_4g_mem_size; > next_base = mem_base + mem_len; > } > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 7c39c913355b..f7da1d5dd40d 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -832,9 +832,10 @@ void pc_memory_init(PCMachineState *pcms, > machine->ram, > x86ms->below_4g_mem_size, > x86ms->above_4g_mem_size); > - memory_region_add_subregion(system_memory, 0x100000000ULL, > + memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, > ram_above_4g); > - e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); > + e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, > + E820_RAM); > } > > if (pcms->sgx_epc.size != 0) { > @@ -875,7 +876,7 @@ void pc_memory_init(PCMachineState *pcms, > machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); > } else { > machine->device_memory->base = > - 0x100000000ULL + x86ms->above_4g_mem_size; > + x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > } > > machine->device_memory->base = > @@ -1019,7 +1020,7 @@ uint64_t pc_pci_hole64_start(void) > } else if (pcms->sgx_epc.size != 0) { > hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); > } else { > - hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; > + hole64_start = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > } > > return ROUND_UP(hole64_start, 1 * GiB); > diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c > index a44d66ba2afc..09d9c7c73d9f 100644 > --- a/hw/i386/sgx.c > +++ b/hw/i386/sgx.c > @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) > return; > } > > - sgx_epc->base = 0x100000000ULL + x86ms->above_4g_mem_size; > + sgx_epc->base = x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; > > memory_region_init(&sgx_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX); > memory_region_add_subregion(get_system_memory(), sgx_epc->base, > diff --git a/hw/i386/x86.c b/hw/i386/x86.c > index 78b05ab7a2d1..af3c790a2830 100644 > --- a/hw/i386/x86.c > +++ b/hw/i386/x86.c > @@ -1373,6 +1373,7 @@ static void x86_machine_initfn(Object *obj) > x86ms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); > x86ms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); > x86ms->bus_lock_ratelimit = 0; > + x86ms->above_4g_mem_start = 0x100000000ULL; s/0x.../4 * GiB/ > } > > static void x86_machine_class_init(ObjectClass *oc, void *data) > diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h > index 9089bdd99c3a..df82c5fd4252 100644 > --- a/include/hw/i386/x86.h > +++ b/include/hw/i386/x86.h > @@ -56,6 +56,9 @@ struct X86MachineState { > /* RAM information (sizes, addresses, configuration): */ > ram_addr_t below_4g_mem_size, above_4g_mem_size; > > + /* Start address of the initial RAM above 4G */ > + uint64_t above_4g_mem_start; > + > /* CPU and apic information: */ > bool apic_xrupt_override; > unsigned pci_irq_mask;