From: Peter Delevoryas <pdel@fb.com>
Cc: <pdel@fb.com>, <zhdaniel@fb.com>, <clg@kaod.org>,
<qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,
<komlodi@google.com>, <titusr@google.com>, <andrew@aj.id.au>,
<joel@jms.id.au>
Subject: [PATCH 04/14] aspeed: i2c: Fix DMA len write-enable bit handling
Date: Mon, 27 Jun 2022 12:54:56 -0700 [thread overview]
Message-ID: <20220627195506.403715-5-pdel@fb.com> (raw)
In-Reply-To: <20220627195506.403715-1-pdel@fb.com>
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I think we should be checking the write-enable bits on the incoming
value, not checking the register array. I'm not sure we're even writing
the write-enable bits to the register array, actually.
[1] https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148
Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/i2c/aspeed_i2c.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 2cfd05cb6c..6c8222717f 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -644,18 +644,18 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
RX_BUF_LEN) + 1;
break;
case A_I2CM_DMA_LEN:
- w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
- ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
+ w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
+ FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
/* If none of the w1t bits are set, just write to the reg as normal. */
if (!w1t) {
bus->regs[R_I2CM_DMA_LEN] = value;
break;
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN));
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN));
}
--
2.30.2
next prev parent reply other threads:[~2022-06-27 19:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 19:54 [PATCH 00/14] aspeed: Add I2C new register DMA slave mode support Peter Delevoryas
2022-06-27 19:54 ` [PATCH 01/14] hw/i2c: support multiple masters Peter Delevoryas
2022-06-27 19:54 ` [PATCH 02/14] hw/i2c: add asynchronous send Peter Delevoryas
2022-06-27 19:54 ` [PATCH 03/14] hw/i2c/aspeed: add slave device in old register mode Peter Delevoryas
2022-06-27 19:54 ` Peter Delevoryas [this message]
2022-06-28 7:01 ` [PATCH 04/14] aspeed: i2c: Fix DMA len write-enable bit handling Cédric Le Goater
2022-06-28 7:05 ` Peter Delevoryas
2022-06-27 19:54 ` [PATCH 05/14] aspeed: i2c: Fix R_I2CD_FUN_CTRL reference Peter Delevoryas
2022-06-28 7:01 ` Cédric Le Goater
2022-06-28 7:05 ` Peter Delevoryas
2022-06-27 19:54 ` [PATCH 07/14] aspeed: Add PECI controller Peter Delevoryas
2022-06-28 6:47 ` Cédric Le Goater
2022-06-28 6:58 ` Peter Delevoryas
2022-06-27 19:55 ` [PATCH 08/14] hw/misc: Add fby35-cpld Peter Delevoryas
2022-06-28 6:50 ` Cédric Le Goater
2022-06-28 7:00 ` Peter Delevoryas
2022-06-27 19:55 ` [PATCH 09/14] pmbus: Reset out buf after switching pages Peter Delevoryas
2022-06-28 6:51 ` Cédric Le Goater
2022-06-28 7:04 ` Peter Delevoryas
2022-06-27 19:55 ` [PATCH 10/14] pmbus: Add read-only IC_DEVICE_ID support Peter Delevoryas
2022-06-27 19:55 ` [PATCH 11/14] aspeed: Add oby35-cl machine Peter Delevoryas
2022-06-27 20:04 ` [PATCH 00/14] aspeed: Add I2C new register DMA slave mode support Peter Delevoryas
2022-06-27 22:27 ` [PATCH 12/14] hw/misc: Add intel-me Peter Delevoryas
2022-06-27 22:27 ` [PATCH 13/14] aspeed: Add intel-me on i2c6 instead of BMC Peter Delevoryas
2022-06-27 22:27 ` [PATCH 14/14] aspeed: Add I2C new register DMA slave mode support Peter Delevoryas
2022-06-28 7:02 ` Cédric Le Goater
2022-06-28 7:06 ` Peter Delevoryas
2022-06-28 6:58 ` [PATCH 12/14] hw/misc: Add intel-me Cédric Le Goater
2022-06-28 7:17 ` Peter Delevoryas
2022-06-28 7:05 ` [PATCH 00/14] aspeed: Add I2C new register DMA slave mode support Cédric Le Goater
2022-06-28 7:16 ` Peter Delevoryas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220627195506.403715-5-pdel@fb.com \
--to=pdel@fb.com \
--cc=andrew@aj.id.au \
--cc=clg@kaod.org \
--cc=joel@jms.id.au \
--cc=komlodi@google.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=titusr@google.com \
--cc=zhdaniel@fb.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).