* [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 10:11 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 02/45] target/arm: Add infrastructure for disas_sme Richard Henderson
` (44 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Dump SVCR, plus use the correct access check for Streaming Mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bb44ad45aa..4a35890853 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -885,6 +885,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int i;
int el = arm_current_el(env);
const char *ns_status;
+ bool sve;
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
for (i = 0; i < 32; i++) {
@@ -911,6 +912,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
el,
psr & PSTATE_SP ? 'h' : 't');
+ if (cpu_isar_feature(aa64_sme, cpu)) {
+ qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
+ env->svcr,
+ (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
+ (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
+ }
if (cpu_isar_feature(aa64_bti, cpu)) {
qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
}
@@ -925,7 +932,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
- if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
+ if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
+ sve = sme_exception_el(env, el) == 0;
+ } else if (cpu_isar_feature(aa64_sve, cpu)) {
+ sve = sve_exception_el(env, el) == 0;
+ } else {
+ sve = false;
+ }
+
+ if (sve) {
int j, zcr_len = sve_vqm1_for_el(env, el);
for (i = 0; i <= FFR_PRED_NUM; i++) {
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state
2022-06-28 4:20 ` [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Richard Henderson
@ 2022-07-01 10:11 ` Peter Maydell
2022-07-03 8:43 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 10:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:25, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Dump SVCR, plus use the correct access check for Streaming Mode.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Dumping the actual ZA storage seems like it would be more
annoying than useful :-)
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* Re: [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state
2022-07-01 10:11 ` Peter Maydell
@ 2022-07-03 8:43 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-03 8:43 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/1/22 15:41, Peter Maydell wrote:
> On Tue, 28 Jun 2022 at 05:25, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Dump SVCR, plus use the correct access check for Streaming Mode.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> Dumping the actual ZA storage seems like it would be more
> annoying than useful :-)
That's what I thought too. ;-)
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 02/45] target/arm: Add infrastructure for disas_sme
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
2022-06-28 4:20 ` [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Richard Henderson
` (43 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 1 +
target/arm/sme.decode | 20 ++++++++++++++++++++
target/arm/translate-a64.c | 7 ++++++-
target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++
target/arm/meson.build | 2 ++
5 files changed, 64 insertions(+), 1 deletion(-)
create mode 100644 target/arm/sme.decode
create mode 100644 target/arm/translate-sme.c
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index f0970c6b8c..789b6e8e78 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s)
}
bool disas_sve(DisasContext *, uint32_t);
+bool disas_sme(DisasContext *, uint32_t);
void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
new file mode 100644
index 0000000000..c25c031a71
--- /dev/null
+++ b/target/arm/sme.decode
@@ -0,0 +1,20 @@
+# AArch64 SME instruction descriptions
+#
+# Copyright (c) 2022 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c86b97b1d4..a5f8a6c771 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14806,7 +14806,12 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
switch (extract32(insn, 25, 4)) {
- case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
+ case 0x0:
+ if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
+ unallocated_encoding(s);
+ }
+ break;
+ case 0x1: case 0x3: /* UNALLOCATED */
unallocated_encoding(s);
break;
case 0x2:
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
new file mode 100644
index 0000000000..786c93fb2d
--- /dev/null
+++ b/target/arm/translate-sme.c
@@ -0,0 +1,35 @@
+/*
+ * AArch64 SME translation
+ *
+ * Copyright (c) 2022 Linaro, Ltd
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "translate.h"
+#include "exec/helper-gen.h"
+#include "translate-a64.h"
+#include "fpu/softfloat.h"
+
+
+/*
+ * Include the generated decoder.
+ */
+
+#include "decode-sme.c.inc"
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 43dc600547..6dd7e93643 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,5 +1,6 @@
gen = [
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
+ decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
@@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'sme_helper.c',
'translate-a64.c',
'translate-sve.c',
+ 'translate-sme.c',
))
arm_softmmu_ss = ss.source_set()
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
2022-06-28 4:20 ` [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Richard Henderson
2022-06-28 4:20 ` [PATCH v4 02/45] target/arm: Add infrastructure for disas_sme Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 11:06 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 04/45] target/arm: Mark ADR as non-streaming Richard Henderson
` (42 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
detection ought to be trivially true, but the pseudocode still contains
a number of conditions, and QEMU has not yet committed to dropping A32
support for EL[12] when v9 features are present.
Since the computation of SME_TRAP_NONSTREAMING is necessarily different
for the two modes, we might as well preserve bits within TBFLAG_ANY and
allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 7 +++
target/arm/translate.h | 4 ++
target/arm/sme-fa64.decode | 89 ++++++++++++++++++++++++++++++++++++++
target/arm/helper.c | 42 ++++++++++++++++++
target/arm/translate-a64.c | 40 ++++++++++++++++-
target/arm/translate-vfp.c | 12 +++++
target/arm/translate.c | 2 +
target/arm/meson.build | 1 +
8 files changed, 195 insertions(+), 2 deletions(-)
create mode 100644 target/arm/sme-fa64.decode
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4a4342f262..9e12669c12 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3146,6 +3146,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
* the same thing as the current security state of the processor!
*/
FIELD(TBFLAG_A32, NS, 10, 1)
+/*
+ * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
+ * This requires an SME trap from AArch32 mode when using NEON.
+ */
+FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
/*
* Bit usage when in AArch32 state, for M-profile only.
@@ -3183,6 +3188,8 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
FIELD(TBFLAG_A64, SVL, 24, 4)
+/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
+FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
/*
* Helpers for using the above.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 22fd882368..cbc907c751 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -102,6 +102,10 @@ typedef struct DisasContext {
bool pstate_sm;
/* True if PSTATE.ZA is set. */
bool pstate_za;
+ /* True if non-streaming insns should raise an SME Streaming exception. */
+ bool sme_trap_nonstreaming;
+ /* True if the current instruction is non-streaming. */
+ bool is_nonstreaming;
/* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
bool mve_no_pred;
/*
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
new file mode 100644
index 0000000000..4c2569477d
--- /dev/null
+++ b/target/arm/sme-fa64.decode
@@ -0,0 +1,89 @@
+# AArch64 SME allowed instruction decoding
+#
+# Copyright (c) 2022 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
+# Arm Architecture Reference Manual Supplement,
+# The Scalable Matrix Extension (SME), for Armv9-A
+
+{
+ [
+ OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0]
+ OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0]
+ OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0]
+ OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0]
+ OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0]
+ OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0]
+ OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0]
+ ]
+ FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations
+}
+
+{
+ [
+ OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar)
+ OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16)
+ OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar)
+ OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
+ ]
+ FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations
+}
+
+FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store
+FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions
+
+# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions
+# We don't actually need to include these, as the default is OK.
+# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations
+# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
+# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal)
+# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
+# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
+# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
+
+FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR
+FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
+FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
+FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS
+FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR
+FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP
+FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
+FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
+FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
+FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
+FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA
+FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA
+FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
+FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
+FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
+FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector)
+FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm)
+FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector)
+FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector)
+FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector)
+FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
+FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
+FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
+FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
+FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch
+FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar)
+FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar)
+FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector)
+FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2886a123a..976e414eda 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6269,6 +6269,32 @@ int sme_exception_el(CPUARMState *env, int el)
return 0;
}
+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
+static bool sme_fa64(CPUARMState *env, int el)
+{
+ if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
+ return false;
+ }
+
+ if (el <= 1 && !el_is_in_host(env, el)) {
+ if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
+ return false;
+ }
+ }
+ if (el <= 2 && arm_is_el2_enabled(env)) {
+ if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
+ return false;
+ }
+ }
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
/*
* Given that SVE is enabled, return the vector length for EL.
*/
@@ -11312,6 +11338,21 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
}
+ /*
+ * The SME exception we are testing for is raised via
+ * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called
+ * when EL1 is using A64 or EL2 using A64 and !TGE.
+ * See AArch32.CheckAdvSIMDOrFPEnabled().
+ */
+ if (el == 0
+ && FIELD_EX64(env->svcr, SVCR, SM)
+ && (!arm_is_el2_enabled(env)
+ || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
+ && arm_el_is_aa64(env, 1)
+ && !sme_fa64(env, el)) {
+ DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
+ }
+
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
@@ -11361,6 +11402,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
}
if (FIELD_EX64(env->svcr, SVCR, SM)) {
DP_TBFLAG_A64(flags, PSTATE_SM, 1);
+ DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
}
DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a5f8a6c771..7fab7f64f8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
* unallocated-encoding checks (otherwise the syndrome information
* for the resulting exception will be incorrect).
*/
-static bool fp_access_check(DisasContext *s)
+static bool fp_access_check_only(DisasContext *s)
{
if (s->fp_excp_el) {
assert(!s->fp_access_checked);
@@ -1170,6 +1170,19 @@ static bool fp_access_check(DisasContext *s)
return true;
}
+static bool fp_access_check(DisasContext *s)
+{
+ if (!fp_access_check_only(s)) {
+ return false;
+ }
+ if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_smetrap(SME_ET_Streaming, false));
+ return false;
+ }
+ return true;
+}
+
/* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
*/
@@ -1994,7 +2007,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
default:
g_assert_not_reached();
}
- if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
+ if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) {
return;
} else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
return;
@@ -14530,6 +14543,23 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
}
}
+/*
+ * Include the generated SME FA64 decoder.
+ */
+
+#include "decode-sme-fa64.c.inc"
+
+static bool trans_OK(DisasContext *s, arg_OK *a)
+{
+ return true;
+}
+
+static bool trans_FAIL(DisasContext *s, arg_OK *a)
+{
+ s->is_nonstreaming = true;
+ return true;
+}
+
/**
* is_guarded_page:
* @env: The cpu environment
@@ -14657,6 +14687,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
+ dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
@@ -14805,6 +14836,11 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
}
+ s->is_nonstreaming = false;
+ if (s->sme_trap_nonstreaming) {
+ disas_sme_fa64(s, insn);
+ }
+
switch (extract32(insn, 25, 4)) {
case 0x0:
if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index 82fdbcae53..bd5ae27d09 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -234,6 +234,18 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
return false;
}
+ /*
+ * Note that rebuild_hflags_a32 has already accounted for being in EL0
+ * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not
+ * appear to be any insns which touch VFP which are allowed.
+ */
+ if (s->sme_trap_nonstreaming) {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_smetrap(SME_ET_Streaming,
+ s->base.pc_next - s->pc_curr == 2));
+ return false;
+ }
+
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
unallocated_encoding(s);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6617de775f..4ffb095c73 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9378,6 +9378,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN);
dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE);
}
+ dc->sme_trap_nonstreaming =
+ EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING);
}
dc->cp_regs = cpu->cp_regs;
dc->features = env->features;
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6dd7e93643..87e911b27f 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
gen = [
decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
+ decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active
2022-06-28 4:20 ` [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Richard Henderson
@ 2022-07-01 11:06 ` Peter Maydell
2022-07-04 8:28 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 11:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This new behaviour is in the ARM pseudocode function
> AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
> via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
> the trap would be delivered is in AArch64 mode.
>
> Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
> detection ought to be trivially true, but the pseudocode still contains
> a number of conditions, and QEMU has not yet committed to dropping A32
> support for EL[12] when v9 features are present.
>
> Since the computation of SME_TRAP_NONSTREAMING is necessarily different
> for the two modes, we might as well preserve bits within TBFLAG_ANY and
> allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> +# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
> +# Arm Architecture Reference Manual Supplement,
> +# The Scalable Matrix Extension (SME), for Armv9-A
> +
> +{
> + [
> + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0]
> + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0]
> + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0]
> + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0]
> + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0]
> + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0]
> + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0]
> + ]
> + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations
> +}
> +
> +{
> + [
> + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar)
> + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16)
> + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar)
> + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
> + ]
> + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations
> +}
> +
> +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store
> +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions
> +
> +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions
> +# We don't actually need to include these, as the default is OK.
> +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations
> +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
> +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal)
> +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
> +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
> +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
Don't we need a FAIL line for the "FJCVTZS should be illegal" case ?
> +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR
> +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
> +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
> +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS
> +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR
> +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP
> +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
> +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
> +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
> +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
> +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA
> +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA
> +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
> +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
> +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
> +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector)
> +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm)
> +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector)
> +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector)
> +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector)
> +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
> +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
> +FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
> +FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
> +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch
> +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar)
> +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar)
> +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector)
> +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc)
> @@ -11312,6 +11338,21 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
> DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
> }
>
> + /*
> + * The SME exception we are testing for is raised via
> + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called
> + * when EL1 is using A64 or EL2 using A64 and !TGE.
> + * See AArch32.CheckAdvSIMDOrFPEnabled().
> + */
> + if (el == 0
> + && FIELD_EX64(env->svcr, SVCR, SM)
> + && (!arm_is_el2_enabled(env)
> + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
> + && arm_el_is_aa64(env, 1)
> + && !sme_fa64(env, el)) {
I can't get any of:
* the logic in the comment
* the logic in the C code
* the logic in the the pseudocode AArch32.CheckAdvSIMDOrFPEnabled()
which causes it to call AArch64.CheckFPEnabled()
to line up with each other.
The comment has:
* (EL1 A64) OR (EL2 A64 && !TGE)
The pseudocode has:
* (!TGE && EL1 A64) OR (TGE && EL2 A64 && EL1 A64)
[seems odd that it is checking the width of EL1 in the TGE case
but I haven't followed the logic through to find out why]
The C code here has:
* (!TGE && EL2 A64 && EL1 A64)
What am I missing ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active
2022-07-01 11:06 ` Peter Maydell
@ 2022-07-04 8:28 ` Richard Henderson
2022-07-04 8:33 ` Peter Maydell
0 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-07-04 8:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/1/22 16:36, Peter Maydell wrote:
>> + /*
>> + * The SME exception we are testing for is raised via
>> + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called
>> + * when EL1 is using A64 or EL2 using A64 and !TGE.
>> + * See AArch32.CheckAdvSIMDOrFPEnabled().
>> + */
>> + if (el == 0
>> + && FIELD_EX64(env->svcr, SVCR, SM)
>> + && (!arm_is_el2_enabled(env)
>> + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
>> + && arm_el_is_aa64(env, 1)
>> + && !sme_fa64(env, el)) {
>
> I can't get any of:
> * the logic in the comment
> * the logic in the C code
> * the logic in the the pseudocode AArch32.CheckAdvSIMDOrFPEnabled()
> which causes it to call AArch64.CheckFPEnabled()
> to line up with each other.
>
> The comment has:
> * (EL1 A64) OR (EL2 A64 && !TGE)
> The pseudocode has:
> * (!TGE && EL1 A64) OR (TGE && EL2 A64 && EL1 A64)
> [seems odd that it is checking the width of EL1 in the TGE case
> but I haven't followed the logic through to find out why]
> The C code here has:
> * (!TGE && EL2 A64 && EL1 A64)
>
> What am I missing ?
I'm looking at 0487H.a... are you looking at a different version?
Because the pseudocode I see isn't what you list above:
> if PSTATE.EL == EL0 && (!EL2Enabled() || (!ELUsingAArch32(EL2) && HCR_EL2.TGE == '0')) &&
> !ELUsingAArch32(EL1) then
So
(!EL2 || (EL2 A64 && !TGE)) && EL1 A64
which is, as far as I can see, what the C code has.
I'll adjust the comment, anyway.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active
2022-07-04 8:28 ` Richard Henderson
@ 2022-07-04 8:33 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 8:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Mon, 4 Jul 2022 at 09:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/1/22 16:36, Peter Maydell wrote:
> >> + /*
> >> + * The SME exception we are testing for is raised via
> >> + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called
> >> + * when EL1 is using A64 or EL2 using A64 and !TGE.
> >> + * See AArch32.CheckAdvSIMDOrFPEnabled().
> >> + */
> >> + if (el == 0
> >> + && FIELD_EX64(env->svcr, SVCR, SM)
> >> + && (!arm_is_el2_enabled(env)
> >> + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
> >> + && arm_el_is_aa64(env, 1)
> >> + && !sme_fa64(env, el)) {
> >
> > I can't get any of:
> > * the logic in the comment
> > * the logic in the C code
> > * the logic in the the pseudocode AArch32.CheckAdvSIMDOrFPEnabled()
> > which causes it to call AArch64.CheckFPEnabled()
> > to line up with each other.
> >
> > The comment has:
> > * (EL1 A64) OR (EL2 A64 && !TGE)
> > The pseudocode has:
> > * (!TGE && EL1 A64) OR (TGE && EL2 A64 && EL1 A64)
> > [seems odd that it is checking the width of EL1 in the TGE case
> > but I haven't followed the logic through to find out why]
> > The C code here has:
> > * (!TGE && EL2 A64 && EL1 A64)
> >
> > What am I missing ?
>
> I'm looking at 0487H.a... are you looking at a different version?
> Because the pseudocode I see isn't what you list above:
>
> > if PSTATE.EL == EL0 && (!EL2Enabled() || (!ELUsingAArch32(EL2) && HCR_EL2.TGE == '0')) &&
>
> > !ELUsingAArch32(EL1) then
> So
> (!EL2 || (EL2 A64 && !TGE)) && EL1 A64
>
> which is, as far as I can see, what the C code has.
Yeah, I misread the pseudocode (it only calls AArch64.CheckFPAdvSIMDEnabled
in the first branch of the if..elsif..., and it's there that the SME check
happens, not in AArch64.CheckFPEnabled(), which is called in both branches).
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 04/45] target/arm: Mark ADR as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (2 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 11:11 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR " Richard Henderson
` (41 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark ADR as a non-streaming instruction, which should trap
if full a64 support is not enabled in streaming mode.
Removing entries from sme-fa64.decode is an easy way to see
what remains to be done.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 7 +++++++
target/arm/sme-fa64.decode | 1 -
target/arm/translate-sve.c | 8 ++++----
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index cbc907c751..e2e619dab2 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -566,4 +566,11 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
+#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
+ { \
+ s->is_nonstreaming = true; \
+ return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
+ }
+
#endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index 4c2569477d..bce717ae5f 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR
FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 62b5f3040c..5d1db0d3ff 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1320,10 +1320,10 @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
}
-TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
-TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
-TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
-TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
+TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
+TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
+TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
+TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
/*
*** SVE Integer Misc - Unpredicated Group
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (3 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 04/45] target/arm: Mark ADR as non-streaming Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 11:15 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL " Richard Henderson
` (40 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 2 --
target/arm/translate-sve.c | 9 ++++++---
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index bce717ae5f..a48f164ed4 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -60,8 +60,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
-FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS
-FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR
FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP
FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 5d1db0d3ff..d6faec15fe 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1785,7 +1785,8 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s)
/* Note pat == 31 is #all, to set all elements. */
-TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false)
+TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve,
+ do_predset, 0, FFR_PRED_NUM, 31, false)
/* Note pat == 32 is #unimp, to set no elements. */
TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false)
@@ -1799,11 +1800,13 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
.rd = a->rd, .pg = a->pg, .s = a->s,
.rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM,
};
+
+ s->is_nonstreaming = true;
return trans_AND_pppp(s, &alt_a);
}
-TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
-TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
+TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
+TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
void (*gen_fn)(TCGv_i32, TCGv_ptr,
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (4 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:14 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA " Richard Henderson
` (39 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/translate-sve.c | 22 ++++++++++++----------
2 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index a48f164ed4..c25bad5ee5 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,9 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA
-FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT
-FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP
FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d6faec15fe..ae48040aa4 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1333,14 +1333,15 @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
NULL, gen_helper_sve_fexpa_h,
gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
};
-TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
- fexpa_fns[a->esz], a->rd, a->rn, 0)
+TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
static gen_helper_gvec_3 * const ftssel_fns[4] = {
NULL, gen_helper_sve_ftssel_h,
gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
};
-TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz,
+ ftssel_fns[a->esz], a, 0)
/*
*** SVE Predicate Logical Operations Group
@@ -2536,7 +2537,8 @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
static gen_helper_gvec_3 * const compact_fns[4] = {
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
};
-TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz,
+ compact_fns[a->esz], a, 0)
/* Call the helper that computes the ARM LastActiveElement pseudocode
* function, scaled by the element size. This includes the not found
@@ -6374,22 +6376,22 @@ static gen_helper_gvec_3 * const bext_fns[4] = {
gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
};
-TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bext_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bext_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const bdep_fns[4] = {
gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
};
-TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bdep_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bdep_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const bgrp_fns[4] = {
gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
};
-TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
- bgrp_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+ bgrp_fns[a->esz], a, 0)
static gen_helper_gvec_3 * const cadd_fns[4] = {
gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
2022-06-28 4:20 ` [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL " Richard Henderson
@ 2022-07-01 12:14 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 12:14 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sme-fa64.decode | 3 ---
> target/arm/translate-sve.c | 22 ++++++++++++----------
> 2 files changed, 12 insertions(+), 13 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (5 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:18 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA " Richard Henderson
` (38 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 2 --
target/arm/translate-sve.c | 18 ++++++++++--------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index c25bad5ee5..c75a94e0fc 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,8 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
-FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA
FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ae48040aa4..130432654e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6194,8 +6194,8 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
}
-TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
-TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
+TRANS_FEAT_NONSTREAMING(PMULLB, aa64_sve2, do_trans_pmull, a, false)
+TRANS_FEAT_NONSTREAMING(PMULLT, aa64_sve2, do_trans_pmull, a, true)
static gen_helper_gvec_3 * const saddw_fns[4] = {
NULL, gen_helper_sve2_saddw_h,
@@ -7125,10 +7125,12 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz)
* SVE Integer Multiply-Add (unpredicated)
*/
-TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
- a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
-TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
- a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
+TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz,
+ gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra,
+ 0, FPST_FPCR)
+TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz,
+ gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra,
+ 0, FPST_FPCR)
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
@@ -7301,8 +7303,8 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
gen_helper_gvec_bfdot_idx, a)
-TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
- gen_helper_gvec_bfmmla, a, 0)
+TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
+ gen_helper_gvec_bfmmla, a, 0)
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming
2022-06-28 4:20 ` [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA " Richard Henderson
@ 2022-07-01 12:18 ` Peter Maydell
2022-07-04 8:48 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 12:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sme-fa64.decode | 2 --
> target/arm/translate-sve.c | 18 ++++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
> index c25bad5ee5..c75a94e0fc 100644
> --- a/target/arm/sme-fa64.decode
> +++ b/target/arm/sme-fa64.decode
> @@ -58,8 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
> # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
> # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
>
> -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
This encoding pattern (as the comment says) covers only the esize = 128 case...
> -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
> -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
> +TRANS_FEAT_NONSTREAMING(PMULLB, aa64_sve2, do_trans_pmull, a, false)
> +TRANS_FEAT_NONSTREAMING(PMULLT, aa64_sve2, do_trans_pmull, a, true)
..but these trans functions cover all the esize values.
In the pseudocode for PMULLB/PMULLT it explicitly does
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
so it is definitely intended to distinguish the 128 bit case
from the 16 and 64 bit ones.
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* Re: [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming
2022-07-01 12:18 ` Peter Maydell
@ 2022-07-04 8:48 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-04 8:48 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/1/22 17:48, Peter Maydell wrote:
> On Tue, 28 Jun 2022 at 05:28, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Mark these as a non-streaming instructions, which should trap
>> if full a64 support is not enabled in streaming mode.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/sme-fa64.decode | 2 --
>> target/arm/translate-sve.c | 18 ++++++++++--------
>> 2 files changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
>> index c25bad5ee5..c75a94e0fc 100644
>> --- a/target/arm/sme-fa64.decode
>> +++ b/target/arm/sme-fa64.decode
>> @@ -58,8 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
>> # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
>> # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
>>
>> -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result)
>
> This encoding pattern (as the comment says) covers only the esize = 128 case...
>
>> -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
>> -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
>> +TRANS_FEAT_NONSTREAMING(PMULLB, aa64_sve2, do_trans_pmull, a, false)
>> +TRANS_FEAT_NONSTREAMING(PMULLT, aa64_sve2, do_trans_pmull, a, true)
>
> ..but these trans functions cover all the esize values.
>
> In the pseudocode for PMULLB/PMULLT it explicitly does
> if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
> so it is definitely intended to distinguish the 128 bit case
> from the 16 and 64 bit ones.
Whoops, too right.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (6 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:21 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA " Richard Henderson
` (37 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/translate-sve.c | 15 +++++++++++----
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index c75a94e0fc..f6e10e4bbe 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,9 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL
-FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD
-FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA
FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA
FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 130432654e..9d0a89215c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3861,9 +3861,9 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
NULL, gen_helper_sve_ftmad_h,
gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
};
-TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
- ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
- a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
+TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
+ ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
/*
*** SVE Floating Point Accumulating Reduction Group
@@ -3886,6 +3886,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -3923,12 +3924,18 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
DO_FP3(FADD_zzz, fadd)
DO_FP3(FSUB_zzz, fsub)
DO_FP3(FMUL_zzz, fmul)
-DO_FP3(FTSMUL, ftsmul)
DO_FP3(FRECPS, recps)
DO_FP3(FRSQRTS, rsqrts)
#undef DO_FP3
+static gen_helper_gvec_3_ptr * const ftsmul_fns[4] = {
+ NULL, gen_helper_gvec_ftsmul_h,
+ gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d
+};
+TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz,
+ ftsmul_fns[a->esz], a, 0)
+
/*
*** SVE Floating Point Arithmetic - Predicated Group
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (7 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:22 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 10/45] target/arm: Mark string/histo/crypto " Richard Henderson
` (36 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 1 -
target/arm/translate-sve.c | 12 ++++++------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index f6e10e4bbe..d3039a8bb2 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA
FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9d0a89215c..7524d713ab 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7298,12 +7298,12 @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true)
TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false)
TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true)
-TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
- gen_helper_gvec_smmla_b, a, 0)
-TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
- gen_helper_gvec_usmmla_b, a, 0)
-TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
- gen_helper_gvec_ummla_b, a, 0)
+TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
+ gen_helper_gvec_smmla_b, a, 0)
+TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
+ gen_helper_gvec_usmmla_b, a, 0)
+TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
+ gen_helper_gvec_ummla_b, a, 0)
TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
gen_helper_gvec_bfdot, a, 0)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 10/45] target/arm: Mark string/histo/crypto as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (8 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:25 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 11/45] target/arm: Mark gather/scatter load/store " Richard Henderson
` (35 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 1 -
target/arm/translate-sve.c | 35 ++++++++++++++++++-----------------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index d3039a8bb2..4683850fa5 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions
FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 7524d713ab..4c28cc9200 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7106,21 +7106,21 @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
static gen_helper_gvec_flags_4 * const match_fns[4] = {
gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
};
-TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
+TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
};
-TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
+TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
static gen_helper_gvec_4 * const histcnt_fns[4] = {
NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
};
-TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
- histcnt_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
+ histcnt_fns[a->esz], a, 0)
-TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
- a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
+TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
+ a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz)
DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz)
@@ -7234,20 +7234,21 @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
-TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
- gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
+TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
+ gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
-TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
- gen_helper_crypto_aese, a, false)
-TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
- gen_helper_crypto_aese, a, true)
+TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
+ gen_helper_crypto_aese, a, false)
+TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
+ gen_helper_crypto_aese, a, true)
-TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
- gen_helper_crypto_sm4e, a, 0)
-TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
- gen_helper_crypto_sm4ekey, a, 0)
+TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
+ gen_helper_crypto_sm4e, a, 0)
+TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
+ gen_helper_crypto_sm4ekey, a, 0)
-TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
+TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz,
+ gen_gvec_rax1, a)
TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 11/45] target/arm: Mark gather/scatter load/store as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (9 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 10/45] target/arm: Mark string/histo/crypto " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:29 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 12/45] target/arm: Mark gather prefetch " Richard Henderson
` (34 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 9 ---------
target/arm/translate-sve.c | 6 ++++++
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index 4683850fa5..711636ed30 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,19 +58,10 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar)
FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector)
-FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm)
-FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector)
-FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector)
-FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector)
FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch
-FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar)
-FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar)
-FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector)
-FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4c28cc9200..a50b2f485b 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
@@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (!sve_access_check(s)) {
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (10 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 11/45] target/arm: Mark gather/scatter load/store " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:31 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 " Richard Henderson
` (33 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap if full
a64 support is not enabled in streaming mode. In this case, introduce
PRF_ns (prefetch non-streaming) to handle the checks.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/sve.decode | 10 +++++-----
target/arm/translate-sve.c | 11 +++++++++++
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index 711636ed30..bc41aa2e2a 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,10 +58,7 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm)
-FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector)
FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
-FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a54feb2f61..908643d7d9 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1183,10 +1183,10 @@ LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
-PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
+PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ----
# SVE 32-bit gather prefetch (vector plus immediate)
-PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
+PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ----
# SVE contiguous prefetch (scalar plus immediate)
PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
@@ -1223,13 +1223,13 @@ LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
@rpri_g_load esz=3
# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
-PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
+PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ----
# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
-PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
+PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ----
# SVE 64-bit gather prefetch (vector plus immediate)
-PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
+PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ----
### SVE Memory Store Group
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a50b2f485b..9c58902b6e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5971,6 +5971,17 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
return true;
}
+static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a)
+{
+ if (!dc_isar_feature(aa64_sve, s)) {
+ return false;
+ }
+ /* Prefetch is a nop within QEMU. */
+ s->is_nonstreaming = true;
+ (void)sve_access_check(s);
+ return true;
+}
+
/*
* Move Prefix
*
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming
2022-06-28 4:20 ` [PATCH v4 12/45] target/arm: Mark gather prefetch " Richard Henderson
@ 2022-07-01 12:31 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 12:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Mark these as a non-streaming instructions, which should trap if full
> a64 support is not enabled in streaming mode. In this case, introduce
> PRF_ns (prefetch non-streaming) to handle the checks.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sme-fa64.decode | 3 ---
> target/arm/sve.decode | 10 +++++-----
> target/arm/translate-sve.c | 11 +++++++++++
> 3 files changed, 16 insertions(+), 8 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (11 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 12/45] target/arm: Mark gather prefetch " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 12:33 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 14/45] target/arm: Mark LD1RO " Richard Henderson
` (32 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 2 --
target/arm/translate-sve.c | 2 ++
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index bc41aa2e2a..7a0b05cf2c 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,7 +58,5 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
-FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9c58902b6e..11874a8e77 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4805,6 +4805,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
@@ -4906,6 +4907,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (sve_access_check(s)) {
int vsz = vec_full_reg_size(s);
int elements = vsz >> dtype_esz[a->dtype];
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (12 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 13:00 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 15/45] target/arm: Add SME enablement checks Richard Henderson
` (31 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/translate-sve.c | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index 7a0b05cf2c..33bbd13bcb 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -57,6 +57,3 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
-
-FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
-FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 11874a8e77..e5e9e1e0ca 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a)
if (a->rm == 31) {
return false;
}
+ s->is_nonstreaming = true;
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
@@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a)
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
return false;
}
+ s->is_nonstreaming = true;
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming
2022-06-28 4:20 ` [PATCH v4 14/45] target/arm: Mark LD1RO " Richard Henderson
@ 2022-07-01 13:00 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 13:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:49, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sme-fa64.decode | 3 ---
> target/arm/translate-sve.c | 2 ++
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
> index 7a0b05cf2c..33bbd13bcb 100644
> --- a/target/arm/sme-fa64.decode
> +++ b/target/arm/sme-fa64.decode
> @@ -57,6 +57,3 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography e
> # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
> # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
> # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
> -
> -FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
> -FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 11874a8e77..e5e9e1e0ca 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a)
> if (a->rm == 31) {
> return false;
> }
> + s->is_nonstreaming = true;
> if (sve_access_check(s)) {
> TCGv_i64 addr = new_tmp_a64(s);
> tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
> @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a)
> if (!dc_isar_feature(aa64_sve_f64mm, s)) {
> return false;
> }
> + s->is_nonstreaming = true;
> if (sve_access_check(s)) {
> TCGv_i64 addr = new_tmp_a64(s);
> tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
The sve.decode lines for these two trans functions:
LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \
@rprr_load_msz nreg=0
LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
don't match up with the FAIL line.
The FAIL lines correspond to unallocated encodings in the decode
tables in the main Arm ARM so we can assume this is an error in the SME
supplement.
We should use the right encoding lines in the original commit of
sme-fa64.decode and mention that in its commit message. They should
I believe be:
FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load &
replicate 32 bytes (scalar+scalar)
FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load &
replicate 32 bytes (scalar+imm)
(differences only in bits [22:21]).
For this patch,
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 15/45] target/arm: Add SME enablement checks
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (13 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 14/45] target/arm: Mark LD1RO " Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 13:05 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 16/45] target/arm: Handle SME in sve_access_check Richard Henderson
` (30 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
These functions will be used to verify that the cpu
is in the correct state for a given instruction.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 21 +++++++++++++++++++++
target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 789b6e8e78..02fb95e019 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -29,6 +29,27 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr);
bool sve_access_check(DisasContext *s);
+bool sme_enabled_check(DisasContext *s);
+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
+
+/* This function corresponds to CheckStreamingSVEEnabled. */
+static inline bool sme_sm_enabled_check(DisasContext *s)
+{
+ return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK);
+}
+
+/* This function corresponds to CheckSMEAndZAEnabled. */
+static inline bool sme_za_enabled_check(DisasContext *s)
+{
+ return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK);
+}
+
+/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */
+static inline bool sme_smza_enabled_check(DisasContext *s)
+{
+ return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
+}
+
TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_size);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7fab7f64f8..b16d81bf19 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1216,6 +1216,40 @@ static bool sme_access_check(DisasContext *s)
return true;
}
+/* This function corresponds to CheckSMEEnabled. */
+bool sme_enabled_check(DisasContext *s)
+{
+ /*
+ * Note that unlike sve_excp_el, we have not constrained sme_excp_el
+ * to be zero when fp_excp_el has priority. This is because we need
+ * sme_excp_el by itself for cpregs access checks.
+ */
+ if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) {
+ s->fp_access_checked = true;
+ return sme_access_check(s);
+ }
+ return fp_access_check_only(s);
+}
+
+/* Common subroutine for CheckSMEAnd*Enabled. */
+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
+{
+ if (!sme_enabled_check(s)) {
+ return false;
+ }
+ if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_smetrap(SME_ET_NotStreaming, false));
+ return false;
+ }
+ if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+ syn_smetrap(SME_ET_InactiveZA, false));
+ return false;
+ }
+ return true;
+}
+
/*
* This utility function is for doing register extension with an
* optional shift. You will likely want to pass a temporary for the
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 16/45] target/arm: Handle SME in sve_access_check
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (14 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 15/45] target/arm: Add SME enablement checks Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 13:07 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Richard Henderson
` (29 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
The pseudocode for CheckSVEEnabled gains a check for Streaming
SVE mode, and for SME present but SVE absent.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b16d81bf19..b7b64f7358 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1183,21 +1183,31 @@ static bool fp_access_check(DisasContext *s)
return true;
}
-/* Check that SVE access is enabled. If it is, return true.
+/*
+ * Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
+ * This function corresponds to CheckSVEEnabled().
*/
bool sve_access_check(DisasContext *s)
{
- if (s->sve_excp_el) {
- assert(!s->sve_access_checked);
- s->sve_access_checked = true;
-
+ if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) {
+ assert(dc_isar_feature(aa64_sme, s));
+ if (!sme_sm_enabled_check(s)) {
+ goto fail_exit;
+ }
+ } else if (s->sve_excp_el) {
gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
syn_sve_access_trap(), s->sve_excp_el);
- return false;
+ goto fail_exit;
}
s->sve_access_checked = true;
return fp_access_check(s);
+
+ fail_exit:
+ /* Assert that we only raise one exception per instruction. */
+ assert(!s->sve_access_checked);
+ s->sve_access_checked = true;
+ return false;
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (15 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 16/45] target/arm: Handle SME in sve_access_check Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 18/45] target/arm: Implement SME ZERO Richard Henderson
` (28 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v4: Add streaming_{vec,pred}_reg_size.
---
target/arm/translate-a64.h | 12 ++++++++++++
target/arm/sve.decode | 5 ++++-
target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 02fb95e019..099d3d11d6 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -128,6 +128,12 @@ static inline int vec_full_reg_size(DisasContext *s)
return s->vl;
}
+/* Return the byte size of the vector register, SVL / 8. */
+static inline int streaming_vec_reg_size(DisasContext *s)
+{
+ return s->svl;
+}
+
/*
* Return the offset info CPUARMState of the predicate vector register Pn.
* Note for this purpose, FFR is P16.
@@ -143,6 +149,12 @@ static inline int pred_full_reg_size(DisasContext *s)
return s->vl >> 3;
}
+/* Return the byte size of the predicate register, SVL / 64. */
+static inline int streaming_pred_reg_size(DisasContext *s)
+{
+ return s->svl >> 3;
+}
+
/*
* Round up the size of a register to a size allowed by
* the tcg vector infrastructure. Any operation which uses this
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 908643d7d9..95af08c139 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
# SVE index generation (register start, register increment)
INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
-### SVE Stack Allocation Group
+### SVE / Streaming SVE Stack Allocation Group
# SVE stack frame adjustment
ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
+ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6
ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
+ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6
# SVE stack frame size
RDVL 00000100 101 11111 01010 imm:s6 rd:5
+RDSVL 00000100 101 11111 01011 imm:s6 rd:5
### SVE Bitwise Shift - Unpredicated Group
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e5e9e1e0ca..9e304f78bc 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
return true;
}
+static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a)
+{
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (sme_enabled_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s));
+ }
+ return true;
+}
+
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
{
if (!dc_isar_feature(aa64_sve, s)) {
@@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
return true;
}
+static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a)
+{
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (sme_enabled_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s));
+ }
+ return true;
+}
+
static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
{
if (!dc_isar_feature(aa64_sve, s)) {
@@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
return true;
}
+static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
+{
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (sme_enabled_check(s)) {
+ TCGv_i64 reg = cpu_reg(s, a->rd);
+ tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s));
+ }
+ return true;
+}
+
/*
*** SVE Compute Vector Address Group
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 18/45] target/arm: Implement SME ZERO
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (16 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 19/45] target/arm: Implement SME MOVA Richard Henderson
` (27 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v4: Fix ZA[] comment in helper_sme_zero.
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 4 ++++
target/arm/sme_helper.c | 25 +++++++++++++++++++++++++
target/arm/translate-sme.c | 13 +++++++++++++
4 files changed, 44 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 3bd48c235f..c4ee1f09e4 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -19,3 +19,5 @@
DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
+
+DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index c25c031a71..6e4483fdce 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -18,3 +18,7 @@
#
# This file is processed by scripts/decodetree.py
#
+
+### SME Misc
+
+ZERO 11000000 00 001 00000000000 imm:8
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index b215725594..eef2df73e1 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
memset(env->zarray, 0, sizeof(env->zarray));
}
}
+
+void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
+{
+ uint32_t i;
+
+ /*
+ * Special case clearing the entire ZA space.
+ * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any
+ * parts of the ZA storage outside of SVL.
+ */
+ if (imm == 0xff) {
+ memset(env->zarray, 0, sizeof(env->zarray));
+ return;
+ }
+
+ /*
+ * Recall that ZAnH.D[m] is spread across ZA[n+8*m],
+ * so each row is discontiguous within ZA[].
+ */
+ for (i = 0; i < svl; i++) {
+ if (imm & (1 << (i % 8))) {
+ memset(&env->zarray[i], 0, svl);
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 786c93fb2d..971504559b 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -33,3 +33,16 @@
*/
#include "decode-sme.c.inc"
+
+
+static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
+{
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (sme_za_enabled_check(s)) {
+ gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm),
+ tcg_constant_i32(streaming_vec_reg_size(s)));
+ }
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 19/45] target/arm: Implement SME MOVA
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (17 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 18/45] target/arm: Implement SME ZERO Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-01 16:19 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 20/45] target/arm: Implement SME LD1, ST1 Richard Henderson
` (26 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 12 ++++
target/arm/helper-sve.h | 2 +
target/arm/translate-a64.h | 8 +++
target/arm/translate.h | 5 ++
target/arm/sme.decode | 15 +++++
target/arm/sme_helper.c | 112 +++++++++++++++++++++++++++++++-
target/arm/sve_helper.c | 12 ++++
target/arm/translate-sme.c | 130 +++++++++++++++++++++++++++++++++++++
8 files changed, 295 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index c4ee1f09e4..154bc73d2e 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -21,3 +21,15 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
+
+/* Move to/from vertical array slices, i.e. columns, so 'c'. */
+DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index dc629f851a..ab0333400f 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 099d3d11d6..2a7fe6e9e7 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -178,6 +178,14 @@ static inline int pred_gvec_reg_size(DisasContext *s)
return size_for_gvec(pred_full_reg_size(s));
}
+/* Return a newly allocated pointer to the predicate register. */
+static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
+{
+ TCGv_ptr ret = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno));
+ return ret;
+}
+
bool disas_sve(DisasContext *, uint32_t);
bool disas_sme(DisasContext *, uint32_t);
diff --git a/target/arm/translate.h b/target/arm/translate.h
index e2e619dab2..af5d4a7086 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -156,6 +156,11 @@ static inline int plus_2(DisasContext *s, int x)
return x + 2;
}
+static inline int plus_12(DisasContext *s, int x)
+{
+ return x + 12;
+}
+
static inline int times_2(DisasContext *s, int x)
{
return x * 2;
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 6e4483fdce..241b4895b7 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -22,3 +22,18 @@
### SME Misc
ZERO 11000000 00 001 00000000000 imm:8
+
+### SME Move into/from Array
+
+%mova_rs 13:2 !function=plus_12
+&mova esz rs pg zr za_imm v:bool to_vec:bool
+
+MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \
+ &mova to_vec=0 rs=%mova_rs
+MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \
+ &mova to_vec=0 rs=%mova_rs esz=4
+
+MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \
+ &mova to_vec=1 rs=%mova_rs
+MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \
+ &mova to_vec=1 rs=%mova_rs esz=4
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index eef2df73e1..95159862de 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -19,8 +19,10 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "internals.h"
+#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
+#include "qemu/int128.h"
+#include "vec_internal.h"
/* ResetSVEState */
void arm_reset_sve_state(CPUARMState *env)
@@ -84,3 +86,111 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
}
}
}
+
+/*
+ * Move Zreg vector to ZArray column.
+ */
+#define DO_MOVA_C(NAME, TYPE, H) \
+void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \
+{ \
+ int i, oprsz = simd_oprsz(desc); \
+ for (i = 0; i < oprsz; ) { \
+ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
+ do { \
+ if (pg & 1) { \
+ *(TYPE *)za = *(TYPE *)(vn + H(i)); \
+ } \
+ za += sizeof(ARMVectorReg) * sizeof(TYPE); \
+ i += sizeof(TYPE); \
+ pg >>= sizeof(TYPE); \
+ } while (i & 15); \
+ } \
+}
+
+DO_MOVA_C(sme_mova_cz_b, uint8_t, H1)
+DO_MOVA_C(sme_mova_cz_h, uint16_t, H2)
+DO_MOVA_C(sme_mova_cz_s, uint32_t, H4)
+
+void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc)
+{
+ int i, oprsz = simd_oprsz(desc) / 8;
+ uint8_t *pg = vg;
+ uint64_t *n = vn;
+ uint64_t *a = za;
+
+ for (i = 0; i < oprsz; i++) {
+ if (pg[H1_2(i)] & 1) {
+ a[i * sizeof(ARMVectorReg)] = n[i];
+ }
+ }
+}
+
+void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc)
+{
+ int i, oprsz = simd_oprsz(desc) / 16;
+ uint16_t *pg = vg;
+ Int128 *n = vn;
+ Int128 *a = za;
+
+ for (i = 0; i < oprsz; i++) {
+ if (pg[H2(i)] & 1) {
+ a[i * sizeof(ARMVectorReg)] = n[i];
+ }
+ }
+}
+
+#undef DO_MOVA_C
+
+/*
+ * Move ZArray column to Zreg vector.
+ */
+#define DO_MOVA_Z(NAME, TYPE, H) \
+void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \
+{ \
+ int i, oprsz = simd_oprsz(desc); \
+ for (i = 0; i < oprsz; ) { \
+ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
+ do { \
+ if (pg & 1) { \
+ *(TYPE *)(vd + H(i)) = *(TYPE *)za; \
+ } \
+ za += sizeof(ARMVectorReg) * sizeof(TYPE); \
+ i += sizeof(TYPE); \
+ pg >>= sizeof(TYPE); \
+ } while (i & 15); \
+ } \
+}
+
+DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1)
+DO_MOVA_Z(sme_mova_zc_h, uint16_t, H2)
+DO_MOVA_Z(sme_mova_zc_s, uint32_t, H4)
+
+void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc)
+{
+ int i, oprsz = simd_oprsz(desc) / 8;
+ uint8_t *pg = vg;
+ uint64_t *d = vd;
+ uint64_t *a = za;
+
+ for (i = 0; i < oprsz; i++) {
+ if (pg[H1_2(i)] & 1) {
+ d[i] = a[i * sizeof(ARMVectorReg)];
+ }
+ }
+}
+
+void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc)
+{
+ int i, oprsz = simd_oprsz(desc) / 16;
+ uint16_t *pg = vg;
+ Int128 *d = vd;
+ Int128 *a = za;
+
+ for (i = 0; i < oprsz; i++, za += sizeof(ARMVectorReg)) {
+ if (pg[H2(i)] & 1) {
+ d[i] = a[i * sizeof(ARMVectorReg)];
+ }
+ }
+}
+
+#undef DO_MOVA_Z
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 1654c0bbf9..9a26f253e0 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm,
}
}
+void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm,
+ void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 16;
+ Int128 *d = vd, *n = vn, *m = vm;
+ uint16_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 1) {
+ d[i] = (pg[H2(i)] & 1 ? n : m)[i];
+ }
+}
+
/* Two operand comparison controlled by a predicate.
* ??? It is very tempting to want to be able to expand this inline
* with x86 instructions, e.g.
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 971504559b..8e6881086b 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -35,6 +35,77 @@
#include "decode-sme.c.inc"
+static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
+ int tile_index, bool vertical)
+{
+ int tile = tile_index >> (4 - esz);
+ int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz);
+ int pos, len, offset;
+ TCGv_i32 t_index;
+ TCGv_ptr addr;
+
+ /* Resolve tile.size[index] to an untyped ZA slice index. */
+ t_index = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs));
+ tcg_gen_addi_i32(t_index, t_index, index);
+
+ len = ctz32(streaming_vec_reg_size(s)) - esz;
+
+ if (vertical) {
+ /*
+ * Compute the offset of the index within the tile:
+ * (index % (svl / size)) * size
+ * = (index % (svl >> esz)) << esz
+ * Perform the power-of-two modulo via extraction of the low @len bits.
+ * Perform the multiply by shifting left by @pos bits.
+ * These two operations are performed simultaneously via deposit.
+ */
+ pos = esz;
+ tcg_gen_deposit_z_i32(t_index, t_index, pos, len);
+
+ /* The tile slice offset within env->zarray is the column offset. */
+ offset = tile;
+
+ /* Include the offset of zarray to make this relative to env. */
+ offset += offsetof(CPUARMState, zarray);
+ tcg_gen_addi_i32(t_index, t_index, offset);
+
+ /*
+ * For big-endian, adjust the column slice offset within
+ * the uint64_t host words that make up env->zarray.
+ * This must wait until index and offset are combined.
+ */
+ if (HOST_BIG_ENDIAN && esz < MO_64) {
+ tcg_gen_xori_i32(t_index, t_index, 8 - (1 << esz));
+ }
+ } else {
+ /*
+ * Compute the offset of the index within the tile:
+ * (index % (svl / size)) * (size * sizeof(row))
+ * = (index % (svl >> esz)) << (esz + log2(sizeof(row)))
+ */
+ pos = esz + ctz32(sizeof(ARMVectorReg));
+ tcg_gen_deposit_z_i32(t_index, t_index, pos, len);
+
+ /* The tile slice offset within env->zarray is the row offset. */
+ offset = tile * sizeof(ARMVectorReg);
+
+ /* Include the offset of zarray to make this relative to env. */
+ offset += offsetof(CPUARMState, zarray);
+ tcg_gen_addi_i32(t_index, t_index, offset);
+
+ /* Row slices need no endian adjustment. */
+ }
+
+ /* Add the offset to env to produce the final pointer. */
+ addr = tcg_temp_new_ptr();
+ tcg_gen_ext_i32_ptr(addr, t_index);
+ tcg_temp_free_i32(t_index);
+ tcg_gen_add_ptr(addr, addr, cpu_env);
+
+ return addr;
+}
+
static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
{
if (!dc_isar_feature(aa64_sme, s)) {
@@ -46,3 +117,62 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
}
return true;
}
+
+static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
+{
+ static gen_helper_gvec_4 * const h_fns[5] = {
+ gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
+ gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d,
+ gen_helper_sve_sel_zpzz_q
+ };
+ static gen_helper_gvec_3 * const cz_fns[5] = {
+ gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h,
+ gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d,
+ gen_helper_sme_mova_cz_q,
+ };
+ static gen_helper_gvec_3 * const zc_fns[5] = {
+ gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h,
+ gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d,
+ gen_helper_sme_mova_zc_q,
+ };
+
+ TCGv_ptr t_za, t_zr, t_pg;
+ TCGv_i32 t_desc;
+ int svl;
+
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
+ t_zr = vec_full_reg_ptr(s, a->zr);
+ t_pg = pred_full_reg_ptr(s, a->pg);
+
+ svl = streaming_vec_reg_size(s);
+ t_desc = tcg_constant_i32(simd_desc(svl, svl, 0));
+
+ if (a->v) {
+ /* Vertical slice -- use sme mova helpers. */
+ if (a->to_vec) {
+ zc_fns[a->esz](t_zr, t_za, t_pg, t_desc);
+ } else {
+ cz_fns[a->esz](t_za, t_zr, t_pg, t_desc);
+ }
+ } else {
+ /* Horizontal slice -- reuse sve sel helpers. */
+ if (a->to_vec) {
+ h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc);
+ } else {
+ h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc);
+ }
+ }
+
+ tcg_temp_free_ptr(t_za);
+ tcg_temp_free_ptr(t_zr);
+ tcg_temp_free_ptr(t_pg);
+
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 19/45] target/arm: Implement SME MOVA
2022-06-28 4:20 ` [PATCH v4 19/45] target/arm: Implement SME MOVA Richard Henderson
@ 2022-07-01 16:19 ` Peter Maydell
2022-07-04 9:08 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-01 16:19 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We can reuse the SVE functions for implementing moves to/from
> horizontal tile slices, but we need new ones for moves to/from
> vertical tile slices.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
> index eef2df73e1..95159862de 100644
> --- a/target/arm/sme_helper.c
> +++ b/target/arm/sme_helper.c
> @@ -19,8 +19,10 @@
>
> #include "qemu/osdep.h"
> #include "cpu.h"
> -#include "internals.h"
Did you mean to delete this #include line ?
> +#include "tcg/tcg-gvec-desc.h"
> #include "exec/helper-proto.h"
> +#include "qemu/int128.h"
> +#include "vec_internal.h"
>
> /* ResetSVEState */
> void arm_reset_sve_state(CPUARMState *env)
> @@ -84,3 +86,111 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
> }
> }
> }
> +
> +/*
> + * Move Zreg vector to ZArray column.
> + */
> +#define DO_MOVA_C(NAME, TYPE, H) \
> +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \
> +{ \
> + int i, oprsz = simd_oprsz(desc); \
> + for (i = 0; i < oprsz; ) { \
> + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
> + do { \
> + if (pg & 1) { \
> + *(TYPE *)za = *(TYPE *)(vn + H(i)); \
> + } \
> + za += sizeof(ARMVectorReg) * sizeof(TYPE); \
> + i += sizeof(TYPE); \
> + pg >>= sizeof(TYPE); \
> + } while (i & 15); \
> + } \
> +}
> +
> +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1)
> +DO_MOVA_C(sme_mova_cz_h, uint16_t, H2)
> +DO_MOVA_C(sme_mova_cz_s, uint32_t, H4)
> +
> +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc)
> +{
> + int i, oprsz = simd_oprsz(desc) / 8;
> + uint8_t *pg = vg;
> + uint64_t *n = vn;
> + uint64_t *a = za;
> +
> + for (i = 0; i < oprsz; i++) {
> + if (pg[H1_2(i)] & 1) {
The documentation of the H macros says
"The H1_<N> macros are used when performing byte arithmetic and then
casting the final pointer to a type of size N."
but we're not casting anything to a 2-byte type, so what's happening here?
> + a[i * sizeof(ARMVectorReg)] = n[i];
> + }
> + }
> +}
> +
> +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc)
> +{
> + int i, oprsz = simd_oprsz(desc) / 16;
> + uint16_t *pg = vg;
> + Int128 *n = vn;
> + Int128 *a = za;
> +
> + for (i = 0; i < oprsz; i++) {
> + if (pg[H2(i)] & 1) {
> + a[i * sizeof(ARMVectorReg)] = n[i];
Is it really OK to do this with an Int128 store? That is
in host-order, but the two halves of a 128-bit quantity
in the ZA array are in architectural order. I suppose the
source also will have them in the architectural order, but
it does look odd, especially uncommented.
> + }
> + }
> +}
> +
> +#undef DO_MOVA_C
> diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
> index 971504559b..8e6881086b 100644
> --- a/target/arm/translate-sme.c
> +++ b/target/arm/translate-sme.c
> @@ -35,6 +35,77 @@
> #include "decode-sme.c.inc"
>
>
> +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
> + int tile_index, bool vertical)
> +{
> + int tile = tile_index >> (4 - esz);
> + int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz);
> + int pos, len, offset;
> + TCGv_i32 t_index;
> + TCGv_ptr addr;
> +
> + /* Resolve tile.size[index] to an untyped ZA slice index. */
> + t_index = tcg_temp_new_i32();
> + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs));
> + tcg_gen_addi_i32(t_index, t_index, index);
This code isn't doing what the comment says; it's just calculating
the (not-yet-taken-MOD-dim) slice index, which does depend on the type.
> +
> + len = ctz32(streaming_vec_reg_size(s)) - esz;
What is this the length of ?
> +
> + if (vertical) {
I ended up reviewing this function from bottom to top because to
me the horizontal case seemed simpler to understand first.
(As a result the review comments might read a bit out-of-order.)
Dunno if that justifies flipping the condition around, though.
> + /*
> + * Compute the offset of the index within the tile:
"byte offset" ?
> + * (index % (svl / size)) * size
> + * = (index % (svl >> esz)) << esz
> + * Perform the power-of-two modulo via extraction of the low @len bits.
> + * Perform the multiply by shifting left by @pos bits.
> + * These two operations are performed simultaneously via deposit.
> + */
> + pos = esz;
> + tcg_gen_deposit_z_i32(t_index, t_index, pos, len);
As an aside, this appears to be "deposit into a zero value", but
I had to go digging in the source to find that out, because we
don't document the semantics of this either in the header file
where this function is declared, or in a doc comment on the
implementation of it, or in tcg/README, or in docs/devel.
We really desperately need to document the interface the TCG
core code provides to frontends, because it's getting further
and further away from "it's functions to emit the IR ops
described in tcg/README, with obvious looking function names"...
> +
> + /* The tile slice offset within env->zarray is the column offset. */
> + offset = tile;
I don't understand why we can just add the tile index
(which is going to be an integer 0, 1, 2..) to a byte offset.
In the horizontal case we add tile * sizeof(ARMVectorReg),
which makes more sense to me.
> +
> + /* Include the offset of zarray to make this relative to env. */
> + offset += offsetof(CPUARMState, zarray);
> + tcg_gen_addi_i32(t_index, t_index, offset);
> +
> + /*
> + * For big-endian, adjust the column slice offset within
> + * the uint64_t host words that make up env->zarray.
> + * This must wait until index and offset are combined.
Why? Neither the byte-offset of the start of the tile nor
the byte offset of zarray in CPUARMState ought to be non-8-aligned.
> + */
> + if (HOST_BIG_ENDIAN && esz < MO_64) {
> + tcg_gen_xori_i32(t_index, t_index, 8 - (1 << esz));
> + }
> + } else {
> + /*
> + * Compute the offset of the index within the tile:
"byte offset", right ?
Also this is doing the "take index MOD dim" that the pseudocode
does as a preceding step at the same time, so we should mention that.
> + * (index % (svl / size)) * (size * sizeof(row))
> + * = (index % (svl >> esz)) << (esz + log2(sizeof(row)))
> + */
> + pos = esz + ctz32(sizeof(ARMVectorReg));
> + tcg_gen_deposit_z_i32(t_index, t_index, pos, len);
> +
> + /* The tile slice offset within env->zarray is the row offset. */
> + offset = tile * sizeof(ARMVectorReg);
> +
> + /* Include the offset of zarray to make this relative to env. */
> + offset += offsetof(CPUARMState, zarray);
> + tcg_gen_addi_i32(t_index, t_index, offset);
> +
> + /* Row slices need no endian adjustment. */
> + }
> +
> + /* Add the offset to env to produce the final pointer. */
> + addr = tcg_temp_new_ptr();
> + tcg_gen_ext_i32_ptr(addr, t_index);
> + tcg_temp_free_i32(t_index);
> + tcg_gen_add_ptr(addr, addr, cpu_env);
> +
> + return addr;
> +}
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 19/45] target/arm: Implement SME MOVA
2022-07-01 16:19 ` Peter Maydell
@ 2022-07-04 9:08 ` Richard Henderson
2022-07-04 9:31 ` Peter Maydell
0 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-07-04 9:08 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/1/22 21:49, Peter Maydell wrote:
> On Tue, 28 Jun 2022 at 05:40, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We can reuse the SVE functions for implementing moves to/from
>> horizontal tile slices, but we need new ones for moves to/from
>> vertical tile slices.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>
>> diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
>> index eef2df73e1..95159862de 100644
>> --- a/target/arm/sme_helper.c
>> +++ b/target/arm/sme_helper.c
>> @@ -19,8 +19,10 @@
>>
>> #include "qemu/osdep.h"
>> #include "cpu.h"
>> -#include "internals.h"
>
> Did you mean to delete this #include line ?
I meant to go back and remove it from whence it came, but kept forgetting.
>> +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc)
>> +{
>> + int i, oprsz = simd_oprsz(desc) / 8;
>> + uint8_t *pg = vg;
>> + uint64_t *n = vn;
>> + uint64_t *a = za;
>> +
>> + for (i = 0; i < oprsz; i++) {
>> + if (pg[H1_2(i)] & 1) {
>
> The documentation of the H macros says
> "The H1_<N> macros are used when performing byte arithmetic and then
> casting the final pointer to a type of size N."
> but we're not casting anything to a 2-byte type, so what's happening here?
Yep, error.
>> +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc)
>> +{
>> + int i, oprsz = simd_oprsz(desc) / 16;
>> + uint16_t *pg = vg;
>> + Int128 *n = vn;
>> + Int128 *a = za;
>> +
>> + for (i = 0; i < oprsz; i++) {
>> + if (pg[H2(i)] & 1) {
>> + a[i * sizeof(ARMVectorReg)] = n[i];
>
> Is it really OK to do this with an Int128 store? That is
> in host-order, but the two halves of a 128-bit quantity
> in the ZA array are in architectural order. I suppose the
> source also will have them in the architectural order, but
> it does look odd, especially uncommented.
Would memcpy be better for you?
>> + /* Resolve tile.size[index] to an untyped ZA slice index. */
>> + t_index = tcg_temp_new_i32();
>> + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs));
>> + tcg_gen_addi_i32(t_index, t_index, index);
>
> This code isn't doing what the comment says; it's just calculating
> the (not-yet-taken-MOD-dim) slice index, which does depend on the type.
I guess the comment applies to a larger section than just these two lines.
>
>> +
>> + len = ctz32(streaming_vec_reg_size(s)) - esz;
>
> What is this the length of ?
The length of the extract, aka the mod.
>> + /* The tile slice offset within env->zarray is the column offset. */
>> + offset = tile;
>
> I don't understand why we can just add the tile index
> (which is going to be an integer 0, 1, 2..) to a byte offset.
> In the horizontal case we add tile * sizeof(ARMVectorReg),
> which makes more sense to me.
Hmm. I think you're right this should be tile * column width, or
offset = tile << esz;
I wish I could compare vs FVP...
>> + /*
>> + * For big-endian, adjust the column slice offset within
>> + * the uint64_t host words that make up env->zarray.
>> + * This must wait until index and offset are combined.
>
> Why? Neither the byte-offset of the start of the tile nor
> the byte offset of zarray in CPUARMState ought to be non-8-aligned.
Columns will not be 8-aligned. On page 38 of 0616A.a, see the illustration of ZA0V.B[22],
which is 6 mod 8.
I'll try and improve the commentary.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 19/45] target/arm: Implement SME MOVA
2022-07-04 9:08 ` Richard Henderson
@ 2022-07-04 9:31 ` Peter Maydell
2022-07-04 9:43 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 9:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Mon, 4 Jul 2022 at 10:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/1/22 21:49, Peter Maydell wrote:
> > On Tue, 28 Jun 2022 at 05:40, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> We can reuse the SVE functions for implementing moves to/from
> >> horizontal tile slices, but we need new ones for moves to/from
> >> vertical tile slices.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc)
> >> +{
> >> + int i, oprsz = simd_oprsz(desc) / 16;
> >> + uint16_t *pg = vg;
> >> + Int128 *n = vn;
> >> + Int128 *a = za;
> >> +
> >> + for (i = 0; i < oprsz; i++) {
> >> + if (pg[H2(i)] & 1) {
> >> + a[i * sizeof(ARMVectorReg)] = n[i];
> >
> > Is it really OK to do this with an Int128 store? That is
> > in host-order, but the two halves of a 128-bit quantity
> > in the ZA array are in architectural order. I suppose the
> > source also will have them in the architectural order, but
> > it does look odd, especially uncommented.
>
> Would memcpy be better for you?
I guess that means we end up doing it all as byte-pointer
arithmetic, which might look worse. I think with a comment
that the two halves of the Int128 might be swapped but this
is OK because we are only copying it will be fine.
> >> + /* Resolve tile.size[index] to an untyped ZA slice index. */
> >> + t_index = tcg_temp_new_i32();
> >> + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs));
> >> + tcg_gen_addi_i32(t_index, t_index, index);
> >
> > This code isn't doing what the comment says; it's just calculating
> > the (not-yet-taken-MOD-dim) slice index, which does depend on the type.
>
> I guess the comment applies to a larger section than just these two lines.
>
> >
> >> +
> >> + len = ctz32(streaming_vec_reg_size(s)) - esz;
> >
> > What is this the length of ?
>
> The length of the extract, aka the mod.
>
> >> + /* The tile slice offset within env->zarray is the column offset. */
> >> + offset = tile;
> >
> > I don't understand why we can just add the tile index
> > (which is going to be an integer 0, 1, 2..) to a byte offset.
> > In the horizontal case we add tile * sizeof(ARMVectorReg),
> > which makes more sense to me.
>
> Hmm. I think you're right this should be tile * column width, or
>
> offset = tile << esz;
>
> I wish I could compare vs FVP...
> >> + /*
> >> + * For big-endian, adjust the column slice offset within
> >> + * the uint64_t host words that make up env->zarray.
> >> + * This must wait until index and offset are combined.
> >
> > Why? Neither the byte-offset of the start of the tile nor
> > the byte offset of zarray in CPUARMState ought to be non-8-aligned.
>
> Columns will not be 8-aligned. On page 38 of 0616A.a, see the illustration of ZA0V.B[22],
> which is 6 mod 8.
Yes, but the column slice number isn't part of offset, it's
in index, so (contra the comment) you could do the xor before
the "add offset to index" if you wanted (ie it doesn't matter
which order we do these things).
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 19/45] target/arm: Implement SME MOVA
2022-07-04 9:31 ` Peter Maydell
@ 2022-07-04 9:43 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-04 9:43 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 15:01, Peter Maydell wrote:
>> Columns will not be 8-aligned. On page 38 of 0616A.a, see the illustration of ZA0V.B[22],
>> which is 6 mod 8.
>
> Yes, but the column slice number isn't part of offset, it's
> in index, so (contra the comment) you could do the xor before
> the "add offset to index" if you wanted (ie it doesn't matter
> which order we do these things).
Oh, whoops, yes.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 20/45] target/arm: Implement SME LD1, ST1
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (18 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 19/45] target/arm: Implement SME MOVA Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-04 10:39 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Richard Henderson
` (25 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 82 +++++
target/arm/sme.decode | 9 +
target/arm/sme_helper.c | 614 +++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 70 +++++
4 files changed, 775 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 154bc73d2e..95f6e88bdd 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -33,3 +33,85 @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 241b4895b7..900e3f2a07 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \
&mova to_vec=1 rs=%mova_rs
MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \
&mova to_vec=1 rs=%mova_rs esz=4
+
+### SME Memory
+
+&ldst esz rs pg rn rm za_imm v:bool st:bool
+
+LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
+ &ldst rs=%mova_rs
+LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
+ &ldst esz=4 rs=%mova_rs
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 95159862de..4ff4e22c2c 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -19,10 +19,14 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "internals.h"
#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+#include "exec/exec-all.h"
#include "qemu/int128.h"
#include "vec_internal.h"
+#include "sve_ldst_internal.h"
/* ResetSVEState */
void arm_reset_sve_state(CPUARMState *env)
@@ -194,3 +198,613 @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc)
}
#undef DO_MOVA_Z
+
+/*
+ * Clear elements in a tile slice comprising len bytes.
+ */
+
+typedef void ClearFn(void *ptr, size_t off, size_t len);
+
+static void clear_horizontal(void *ptr, size_t off, size_t len)
+{
+ memset(ptr + off, 0, len);
+}
+
+static void clear_vertical_b(void *vptr, size_t off, size_t len)
+{
+ uint8_t *ptr = vptr;
+ size_t i;
+
+ for (i = 0; i < len; ++i) {
+ ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
+ }
+}
+
+static void clear_vertical_h(void *vptr, size_t off, size_t len)
+{
+ uint16_t *ptr = vptr;
+ size_t i;
+
+ for (i = 0; i < len / 2; ++i) {
+ ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
+ }
+}
+
+static void clear_vertical_s(void *vptr, size_t off, size_t len)
+{
+ uint32_t *ptr = vptr;
+ size_t i;
+
+ for (i = 0; i < len / 4; ++i) {
+ ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
+ }
+}
+
+static void clear_vertical_d(void *vptr, size_t off, size_t len)
+{
+ uint64_t *ptr = vptr;
+ size_t i;
+
+ for (i = 0; i < len / 8; ++i) {
+ ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
+ }
+}
+
+static void clear_vertical_q(void *vptr, size_t off, size_t len)
+{
+ Int128 *ptr = vptr, zero = int128_zero();
+ size_t i;
+
+ for (i = 0; i < len / 16; ++i) {
+ ptr[(i + off) * sizeof(ARMVectorReg)] = zero;
+ }
+}
+
+/*
+ * Copy elements from an array into a tile slice comprising len bytes.
+ */
+
+typedef void CopyFn(void *dst, const void *src, size_t len);
+
+static void copy_horizontal(void *dst, const void *src, size_t len)
+{
+ memcpy(dst, src, len);
+}
+
+static void copy_vertical_b(void *vdst, const void *vsrc, size_t len)
+{
+ const uint8_t *src = vsrc;
+ uint8_t *dst = vdst;
+ size_t i;
+
+ for (i = 0; i < len; ++i) {
+ dst[i * sizeof(ARMVectorReg)] = src[i];
+ }
+}
+
+static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
+{
+ const uint16_t *src = vsrc;
+ uint16_t *dst = vdst;
+ size_t i;
+
+ for (i = 0; i < len / 2; ++i) {
+ dst[i * sizeof(ARMVectorReg)] = src[i];
+ }
+}
+
+static void copy_vertical_s(void *vdst, const void *vsrc, size_t len)
+{
+ const uint32_t *src = vsrc;
+ uint32_t *dst = vdst;
+ size_t i;
+
+ for (i = 0; i < len / 4; ++i) {
+ dst[i * sizeof(ARMVectorReg)] = src[i];
+ }
+}
+
+static void copy_vertical_d(void *vdst, const void *vsrc, size_t len)
+{
+ const uint64_t *src = vsrc;
+ uint64_t *dst = vdst;
+ size_t i;
+
+ for (i = 0; i < len / 8; ++i) {
+ dst[i * sizeof(ARMVectorReg)] = src[i];
+ }
+}
+
+static void copy_vertical_q(void *vdst, const void *vsrc, size_t len)
+{
+ const Int128 *src = vsrc;
+ Int128 *dst = vdst;
+ size_t i;
+
+ for (i = 0; i < len / 16; ++i) {
+ dst[i * sizeof(ARMVectorReg)] = src[i];
+ }
+}
+
+/*
+ * Host and TLB primitives for vertical tile slice addressing.
+ */
+
+#define DO_LD(NAME, TYPE, HOST, TLB) \
+static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \
+{ \
+ TYPE val = HOST(host); \
+ *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
+} \
+static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \
+ intptr_t off, target_ulong addr, uintptr_t ra) \
+{ \
+ TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \
+ *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
+}
+
+#define DO_ST(NAME, TYPE, HOST, TLB) \
+static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \
+{ \
+ TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \
+ HOST(host, val); \
+} \
+static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \
+ intptr_t off, target_ulong addr, uintptr_t ra) \
+{ \
+ TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \
+ TLB(env, useronly_clean_ptr(addr), val, ra); \
+}
+
+/*
+ * The ARMVectorReg elements are stored in host-endian 64-bit units.
+ * For 128-bit quantities, the sequence defined by the Elem[] pseudocode
+ * corresponds to storing the two 64-bit pieces in little-endian order.
+ */
+#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \
+static inline void HNAME##_host(void *za, intptr_t off, void *host) \
+{ \
+ uint64_t val0 = HOST(host), val1 = HOST(host + 8); \
+ uint64_t *ptr = za + off; \
+ ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \
+} \
+static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \
+{ \
+ HNAME##_host(za, off * sizeof(ARMVectorReg), host); \
+} \
+static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \
+ target_ulong addr, uintptr_t ra) \
+{ \
+ uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \
+ uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \
+ uint64_t *ptr = za + off; \
+ ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \
+} \
+static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \
+ target_ulong addr, uintptr_t ra) \
+{ \
+ HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \
+}
+
+#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \
+static inline void HNAME##_host(void *za, intptr_t off, void *host) \
+{ \
+ uint64_t *ptr = za + off; \
+ HOST(host, ptr[BE]); \
+ HOST(host + 1, ptr[!BE]); \
+} \
+static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \
+{ \
+ HNAME##_host(za, off * sizeof(ARMVectorReg), host); \
+} \
+static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \
+ target_ulong addr, uintptr_t ra) \
+{ \
+ uint64_t *ptr = za + off; \
+ TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \
+ TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \
+} \
+static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \
+ target_ulong addr, uintptr_t ra) \
+{ \
+ HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \
+}
+
+DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra)
+DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra)
+DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra)
+DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra)
+DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra)
+DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra)
+DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra)
+
+DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra)
+DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra)
+
+DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra)
+DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra)
+DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra)
+DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra)
+DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra)
+DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra)
+DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra)
+
+DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra)
+DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra)
+
+#undef DO_LD
+#undef DO_ST
+#undef DO_LDQ
+#undef DO_STQ
+
+/*
+ * Common helper for all contiguous predicated loads.
+ */
+
+static inline QEMU_ALWAYS_INLINE
+void sme_ld1(CPUARMState *env, void *za, uint64_t *vg,
+ const target_ulong addr, uint32_t desc, const uintptr_t ra,
+ const int esz, uint32_t mtedesc, bool vertical,
+ sve_ldst1_host_fn *host_fn,
+ sve_ldst1_tlb_fn *tlb_fn,
+ ClearFn *clr_fn,
+ CopyFn *cpy_fn)
+{
+ const intptr_t reg_max = simd_oprsz(desc);
+ const intptr_t esize = 1 << esz;
+ intptr_t reg_off, reg_last;
+ SVEContLdSt info;
+ void *host;
+ int flags;
+
+ /* Find the active elements. */
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
+ /* The entire predicate was false; no load occurs. */
+ clr_fn(za, 0, reg_max);
+ return;
+ }
+
+ /* Probe the page(s). Exit with exception for any invalid page. */
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra);
+
+ /* Handle watchpoints for all active elements. */
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
+ BP_MEM_READ, ra);
+
+ /*
+ * Handle mte checks for all active elements.
+ * Since TBI must be set for MTE, !mtedesc => !mte_active.
+ */
+ if (mtedesc) {
+ sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
+ mtedesc, ra);
+ }
+
+ flags = info.page[0].flags | info.page[1].flags;
+ if (unlikely(flags != 0)) {
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ /*
+ * At least one page includes MMIO.
+ * Any bus operation can fail with cpu_transaction_failed,
+ * which for ARM will raise SyncExternal. Perform the load
+ * into scratch memory to preserve register state until the end.
+ */
+ ARMVectorReg scratch = { };
+
+ reg_off = info.reg_off_first[0];
+ reg_last = info.reg_off_last[1];
+ if (reg_last < 0) {
+ reg_last = info.reg_off_split;
+ if (reg_last < 0) {
+ reg_last = info.reg_off_last[0];
+ }
+ }
+
+ do {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ tlb_fn(env, &scratch, reg_off, addr + reg_off, ra);
+ }
+ reg_off += esize;
+ } while (reg_off & 63);
+ } while (reg_off <= reg_last);
+
+ cpy_fn(za, &scratch, reg_max);
+ return;
+#endif
+ }
+
+ /* The entire operation is in RAM, on valid pages. */
+
+ reg_off = info.reg_off_first[0];
+ reg_last = info.reg_off_last[0];
+ host = info.page[0].host;
+
+ if (!vertical) {
+ memset(za, 0, reg_max);
+ } else if (reg_off) {
+ clr_fn(za, 0, reg_off);
+ }
+
+ while (reg_off <= reg_last) {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ host_fn(za, reg_off, host + reg_off);
+ } else if (vertical) {
+ clr_fn(za, reg_off, esize);
+ }
+ reg_off += esize;
+ } while (reg_off <= reg_last && (reg_off & 63));
+ }
+
+ /*
+ * Use the slow path to manage the cross-page misalignment.
+ * But we know this is RAM and cannot trap.
+ */
+ reg_off = info.reg_off_split;
+ if (unlikely(reg_off >= 0)) {
+ tlb_fn(env, za, reg_off, addr + reg_off, ra);
+ }
+
+ reg_off = info.reg_off_first[1];
+ if (unlikely(reg_off >= 0)) {
+ reg_last = info.reg_off_last[1];
+ host = info.page[1].host;
+
+ do {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ host_fn(za, reg_off, host + reg_off);
+ } else if (vertical) {
+ clr_fn(za, reg_off, esize);
+ }
+ reg_off += esize;
+ } while (reg_off & 63);
+ } while (reg_off <= reg_last);
+ }
+}
+
+static inline QEMU_ALWAYS_INLINE
+void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
+ target_ulong addr, uint32_t desc, uintptr_t ra,
+ const int esz, bool vertical,
+ sve_ldst1_host_fn *host_fn,
+ sve_ldst1_tlb_fn *tlb_fn,
+ ClearFn *clr_fn,
+ CopyFn *cpy_fn)
+{
+ uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+ int bit55 = extract64(addr, 55, 1);
+
+ /* Remove mtedesc from the normal sve descriptor. */
+ desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+
+ /* Perform gross MTE suppression early. */
+ if (!tbi_check(desc, bit55) ||
+ tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+ mtedesc = 0;
+ }
+
+ sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical,
+ host_fn, tlb_fn, clr_fn, cpy_fn);
+}
+
+#define DO_LD(L, END, ESZ) \
+void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \
+ sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \
+ clear_horizontal, copy_horizontal); \
+} \
+void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \
+ sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \
+ clear_vertical_##L, copy_vertical_##L); \
+} \
+void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \
+ sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \
+ clear_horizontal, copy_horizontal); \
+} \
+void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \
+ sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \
+ clear_vertical_##L, copy_vertical_##L); \
+}
+
+DO_LD(b, , MO_8)
+DO_LD(h, _be, MO_16)
+DO_LD(h, _le, MO_16)
+DO_LD(s, _be, MO_32)
+DO_LD(s, _le, MO_32)
+DO_LD(d, _be, MO_64)
+DO_LD(d, _le, MO_64)
+DO_LD(q, _be, MO_128)
+DO_LD(q, _le, MO_128)
+
+#undef DO_LD
+
+/*
+ * Common helper for all contiguous predicated stores.
+ */
+
+static inline QEMU_ALWAYS_INLINE
+void sme_st1(CPUARMState *env, void *za, uint64_t *vg,
+ const target_ulong addr, uint32_t desc, const uintptr_t ra,
+ const int esz, uint32_t mtedesc, bool vertical,
+ sve_ldst1_host_fn *host_fn,
+ sve_ldst1_tlb_fn *tlb_fn)
+{
+ const intptr_t reg_max = simd_oprsz(desc);
+ const intptr_t esize = 1 << esz;
+ intptr_t reg_off, reg_last;
+ SVEContLdSt info;
+ void *host;
+ int flags;
+
+ /* Find the active elements. */
+ if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
+ /* The entire predicate was false; no store occurs. */
+ return;
+ }
+
+ /* Probe the page(s). Exit with exception for any invalid page. */
+ sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra);
+
+ /* Handle watchpoints for all active elements. */
+ sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
+ BP_MEM_WRITE, ra);
+
+ /*
+ * Handle mte checks for all active elements.
+ * Since TBI must be set for MTE, !mtedesc => !mte_active.
+ */
+ if (mtedesc) {
+ sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
+ mtedesc, ra);
+ }
+
+ flags = info.page[0].flags | info.page[1].flags;
+ if (unlikely(flags != 0)) {
+#ifdef CONFIG_USER_ONLY
+ g_assert_not_reached();
+#else
+ /*
+ * At least one page includes MMIO.
+ * Any bus operation can fail with cpu_transaction_failed,
+ * which for ARM will raise SyncExternal. We cannot avoid
+ * this fault and will leave with the store incomplete.
+ */
+ reg_off = info.reg_off_first[0];
+ reg_last = info.reg_off_last[1];
+ if (reg_last < 0) {
+ reg_last = info.reg_off_split;
+ if (reg_last < 0) {
+ reg_last = info.reg_off_last[0];
+ }
+ }
+
+ do {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ tlb_fn(env, za, reg_off, addr + reg_off, ra);
+ }
+ reg_off += esize;
+ } while (reg_off & 63);
+ } while (reg_off <= reg_last);
+ return;
+#endif
+ }
+
+ reg_off = info.reg_off_first[0];
+ reg_last = info.reg_off_last[0];
+ host = info.page[0].host;
+
+ while (reg_off <= reg_last) {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ host_fn(za, reg_off, host + reg_off);
+ }
+ reg_off += 1 << esz;
+ } while (reg_off <= reg_last && (reg_off & 63));
+ }
+
+ /*
+ * Use the slow path to manage the cross-page misalignment.
+ * But we know this is RAM and cannot trap.
+ */
+ reg_off = info.reg_off_split;
+ if (unlikely(reg_off >= 0)) {
+ tlb_fn(env, za, reg_off, addr + reg_off, ra);
+ }
+
+ reg_off = info.reg_off_first[1];
+ if (unlikely(reg_off >= 0)) {
+ reg_last = info.reg_off_last[1];
+ host = info.page[1].host;
+
+ do {
+ uint64_t pg = vg[reg_off >> 6];
+ do {
+ if ((pg >> (reg_off & 63)) & 1) {
+ host_fn(za, reg_off, host + reg_off);
+ }
+ reg_off += 1 << esz;
+ } while (reg_off & 63);
+ } while (reg_off <= reg_last);
+ }
+}
+
+static inline QEMU_ALWAYS_INLINE
+void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
+ uint32_t desc, uintptr_t ra, int esz, bool vertical,
+ sve_ldst1_host_fn *host_fn,
+ sve_ldst1_tlb_fn *tlb_fn)
+{
+ uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+ int bit55 = extract64(addr, 55, 1);
+
+ /* Remove mtedesc from the normal sve descriptor. */
+ desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+
+ /* Perform gross MTE suppression early. */
+ if (!tbi_check(desc, bit55) ||
+ tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+ mtedesc = 0;
+ }
+
+ sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc,
+ vertical, host_fn, tlb_fn);
+}
+
+#define DO_ST(L, END, ESZ) \
+void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \
+ sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \
+} \
+void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \
+ sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \
+} \
+void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \
+ sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \
+} \
+void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
+ target_ulong addr, uint32_t desc) \
+{ \
+ sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \
+ sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \
+}
+
+DO_ST(b, , MO_8)
+DO_ST(h, _be, MO_16)
+DO_ST(h, _le, MO_16)
+DO_ST(s, _be, MO_32)
+DO_ST(s, _le, MO_32)
+DO_ST(d, _be, MO_64)
+DO_ST(d, _le, MO_64)
+DO_ST(q, _be, MO_128)
+DO_ST(q, _le, MO_128)
+
+#undef DO_ST
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 8e6881086b..f9846f137f 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -176,3 +176,73 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
return true;
}
+
+static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
+{
+ typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32);
+
+ /*
+ * Indexed by [esz][be][v][mte][st], which is (except for load/store)
+ * also the order in which the elements appear in the function names,
+ * and so how we must concatenate the pieces.
+ */
+
+#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F }
+#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) }
+#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) }
+#define FN_END(L, B) { FN_HV(L), FN_HV(B) }
+
+ static GenLdSt1 * const fns[5][2][2][2][2] = {
+ FN_END(b, b),
+ FN_END(h_le, h_be),
+ FN_END(s_le, s_be),
+ FN_END(d_le, d_be),
+ FN_END(q_le, q_be),
+ };
+
+#undef FN_LS
+#undef FN_MTE
+#undef FN_HV
+#undef FN_END
+
+ TCGv_ptr t_za, t_pg;
+ TCGv_i64 addr;
+ int svl, desc = 0;
+ bool be = s->be_data == MO_BE;
+ bool mte = s->mte_active[0];
+
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
+ t_pg = pred_full_reg_ptr(s, a->pg);
+ addr = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
+ tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
+
+ if (mte) {
+ desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
+ desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
+ desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
+ desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
+ desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
+ desc <<= SVE_MTEDESC_SHIFT;
+ } else {
+ addr = clean_data_tbi(s, addr);
+ }
+ svl = streaming_vec_reg_size(s);
+ desc = simd_desc(svl, svl, desc);
+
+ fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
+ tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(t_za);
+ tcg_temp_free_ptr(t_pg);
+ tcg_temp_free_i64(addr);
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 20/45] target/arm: Implement SME LD1, ST1
2022-06-28 4:20 ` [PATCH v4 20/45] target/arm: Implement SME LD1, ST1 Richard Henderson
@ 2022-07-04 10:39 ` Peter Maydell
2022-07-05 1:49 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 10:39 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:34, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
> because those functions accept only a Zreg register number.
> For SME, we want to pass a pointer into ZA storage.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> +
> +/*
> + * Clear elements in a tile slice comprising len bytes.
> + */
> +
> +typedef void ClearFn(void *ptr, size_t off, size_t len);
> +
> +static void clear_horizontal(void *ptr, size_t off, size_t len)
> +{
> + memset(ptr + off, 0, len);
> +}
> +
> +static void clear_vertical_b(void *vptr, size_t off, size_t len)
> +{
> + uint8_t *ptr = vptr;
> + size_t i;
> +
> + for (i = 0; i < len; ++i) {
> + ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
> + }
> +}
> +
> +static void clear_vertical_h(void *vptr, size_t off, size_t len)
> +{
> + uint16_t *ptr = vptr;
> + size_t i;
> +
> + for (i = 0; i < len / 2; ++i) {
> + ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
> + }
The code for the bigger-than-byte vertical actions seems wrong:
because 'ptr' is a uint16_t here this expression is mixing
byte offsets (off, the multiply by sizeof(ARMVectorReg) with
halfword offsets (i, the fact we're calculating an index value
for a uint16_t array).
> +}
> +
> +static void clear_vertical_s(void *vptr, size_t off, size_t len)
> +{
> + uint32_t *ptr = vptr;
> + size_t i;
> +
> + for (i = 0; i < len / 4; ++i) {
> + ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
> + }
> +}
> +
> +static void clear_vertical_d(void *vptr, size_t off, size_t len)
> +{
> + uint64_t *ptr = vptr;
> + size_t i;
> +
> + for (i = 0; i < len / 8; ++i) {
> + ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
> + }
> +}
> +
> +static void clear_vertical_q(void *vptr, size_t off, size_t len)
> +{
> + Int128 *ptr = vptr, zero = int128_zero();
> + size_t i;
> +
> + for (i = 0; i < len / 16; ++i) {
> + ptr[(i + off) * sizeof(ARMVectorReg)] = zero;
> + }
> +}
> +
> +/*
> + * Copy elements from an array into a tile slice comprising len bytes.
> + */
> +
> +typedef void CopyFn(void *dst, const void *src, size_t len);
> +
> +static void copy_horizontal(void *dst, const void *src, size_t len)
> +{
> + memcpy(dst, src, len);
> +}
> +
> +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len)
> +{
> + const uint8_t *src = vsrc;
> + uint8_t *dst = vdst;
> + size_t i;
> +
> + for (i = 0; i < len; ++i) {
> + dst[i * sizeof(ARMVectorReg)] = src[i];
> + }
> +}
> +
> +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
> +{
> + const uint16_t *src = vsrc;
> + uint16_t *dst = vdst;
> + size_t i;
> +
> + for (i = 0; i < len / 2; ++i) {
> + dst[i * sizeof(ARMVectorReg)] = src[i];
Similarly the array index calculation for dst[] here looks wrong.
> + }
> +}
> +
> +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len)
> +{
> + const uint32_t *src = vsrc;
> + uint32_t *dst = vdst;
> + size_t i;
> +
> + for (i = 0; i < len / 4; ++i) {
> + dst[i * sizeof(ARMVectorReg)] = src[i];
> + }
> +}
> +
> +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len)
> +{
> + const uint64_t *src = vsrc;
> + uint64_t *dst = vdst;
> + size_t i;
> +
> + for (i = 0; i < len / 8; ++i) {
> + dst[i * sizeof(ARMVectorReg)] = src[i];
> + }
> +}
> +
> +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len)
> +{
> + const Int128 *src = vsrc;
> + Int128 *dst = vdst;
> + size_t i;
> +
> + for (i = 0; i < len / 16; ++i) {
> + dst[i * sizeof(ARMVectorReg)] = src[i];
> + }
> +}
> +
> +/*
> + * Host and TLB primitives for vertical tile slice addressing.
> + */
> +
> +#define DO_LD(NAME, TYPE, HOST, TLB) \
> +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \
> +{ \
> + TYPE val = HOST(host); \
> + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
> +} \
> +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \
> + intptr_t off, target_ulong addr, uintptr_t ra) \
> +{ \
> + TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \
> + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
> +}
So in these functions is 'za' pre-adjusted to the start address of the
vertical column? Is 'off' a byte offset here (in which case the
arithmetic is wrong for anything except byte columns) or has it
been adjusted in the caller to be the index within the column?
(I can't see anything doing the adjustment in the caller but I might
have got tangled up in the macros :-))
> +
> +#define DO_ST(NAME, TYPE, HOST, TLB) \
> +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \
> +{ \
> + TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \
> + HOST(host, val); \
> +} \
> +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \
> + intptr_t off, target_ulong addr, uintptr_t ra) \
> +{ \
> + TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \
> + TLB(env, useronly_clean_ptr(addr), val, ra); \
> +}
> +
> +/*
> + * The ARMVectorReg elements are stored in host-endian 64-bit units.
> + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode
> + * corresponds to storing the two 64-bit pieces in little-endian order.
> + */
> +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \
> +static inline void HNAME##_host(void *za, intptr_t off, void *host) \
> +{ \
> + uint64_t val0 = HOST(host), val1 = HOST(host + 8); \
> + uint64_t *ptr = za + off; \
> + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \
> +} \
> +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \
> +{ \
> + HNAME##_host(za, off * sizeof(ARMVectorReg), host); \
> +} \
> +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \
> + target_ulong addr, uintptr_t ra) \
> +{ \
> + uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \
> + uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \
> + uint64_t *ptr = za + off; \
> + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \
> +} \
> +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \
> + target_ulong addr, uintptr_t ra) \
> +{ \
> + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \
> +}
> +
> +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \
> +static inline void HNAME##_host(void *za, intptr_t off, void *host) \
> +{ \
> + uint64_t *ptr = za + off; \
> + HOST(host, ptr[BE]); \
> + HOST(host + 1, ptr[!BE]); \
> +} \
> +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \
> +{ \
> + HNAME##_host(za, off * sizeof(ARMVectorReg), host); \
> +} \
> +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \
> + target_ulong addr, uintptr_t ra) \
> +{ \
> + uint64_t *ptr = za + off; \
> + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \
> + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \
> +} \
> +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \
> + target_ulong addr, uintptr_t ra) \
> +{ \
> + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \
> +}
> +
> +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
> +{
> + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32);
> +
> + /*
> + * Indexed by [esz][be][v][mte][st], which is (except for load/store)
> + * also the order in which the elements appear in the function names,
> + * and so how we must concatenate the pieces.
> + */
> +
> +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F }
> +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) }
> +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) }
> +#define FN_END(L, B) { FN_HV(L), FN_HV(B) }
> +
> + static GenLdSt1 * const fns[5][2][2][2][2] = {
> + FN_END(b, b),
> + FN_END(h_le, h_be),
> + FN_END(s_le, s_be),
> + FN_END(d_le, d_be),
> + FN_END(q_le, q_be),
> + };
> +
> +#undef FN_LS
> +#undef FN_MTE
> +#undef FN_HV
> +#undef FN_END
> +
> + TCGv_ptr t_za, t_pg;
> + TCGv_i64 addr;
> + int svl, desc = 0;
> + bool be = s->be_data == MO_BE;
> + bool mte = s->mte_active[0];
> +
> + if (!dc_isar_feature(aa64_sme, s)) {
> + return false;
> + }
> + if (!sme_smza_enabled_check(s)) {
> + return true;
> + }
> +
> + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
> + t_pg = pred_full_reg_ptr(s, a->pg);
> + addr = tcg_temp_new_i64();
> +
> + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
> + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
Theoretically we ought to call gen_check_sp_alignment() here
for rn == 31, but I guess we didn't do that for any of the
non-base-A64 instructions like SVE either.
> +
> + if (mte) {
> + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
> + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
> + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
> + desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
> + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
> + desc <<= SVE_MTEDESC_SHIFT;
> + } else {
> + addr = clean_data_tbi(s, addr);
> + }
> + svl = streaming_vec_reg_size(s);
> + desc = simd_desc(svl, svl, desc);
> +
> + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
> + tcg_constant_i32(desc));
> +
> + tcg_temp_free_ptr(t_za);
> + tcg_temp_free_ptr(t_pg);
> + tcg_temp_free_i64(addr);
> + return true;
> +}
> --
> 2.34.1
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 20/45] target/arm: Implement SME LD1, ST1
2022-07-04 10:39 ` Peter Maydell
@ 2022-07-05 1:49 ` Richard Henderson
2022-07-05 10:48 ` Peter Maydell
0 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 1:49 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 16:09, Peter Maydell wrote:
>> +static void clear_vertical_h(void *vptr, size_t off, size_t len)
>> +{
>> + uint16_t *ptr = vptr;
>> + size_t i;
>> +
>> + for (i = 0; i < len / 2; ++i) {
>> + ptr[(i + off) * sizeof(ARMVectorReg)] = 0;
>> + }
>
> The code for the bigger-than-byte vertical actions seems wrong:
> because 'ptr' is a uint16_t here this expression is mixing
> byte offsets (off, the multiply by sizeof(ARMVectorReg) with
> halfword offsets (i, the fact we're calculating an index value
> for a uint16_t array).
I agree these are wrong, because they mix 'i' as index and 'off' as byte offset. I think
the correct addressing is always the same as byte addressing. I.e.
for (i = 0; i < len; i += N) {
uintN_t *ptr = vptr + (i + off) * sizeof(ARMVectorReg);
*ptr = 0;
}
so that every iteration advances N rows and writes N bytes.
>> +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
>> +{
>> + const uint16_t *src = vsrc;
>> + uint16_t *dst = vdst;
>> + size_t i;
>> +
>> + for (i = 0; i < len / 2; ++i) {
>> + dst[i * sizeof(ARMVectorReg)] = src[i];
>
> Similarly the array index calculation for dst[] here looks wrong.
I don't think so in this case. I'm not mixing indexes and byte offsets like I was above.
Recall that the next vertical tile element is not in the next physical row, but in the Nth
physical row. Therefore there are always sizeof(ARMVectorReg) elements in the host layout
between vertical tile elements.
I agree it looks strange.
>> +#define DO_LD(NAME, TYPE, HOST, TLB) \
>> +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \
>> +{ \
>> + TYPE val = HOST(host); \
>> + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
>> +} \
>> +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \
>> + intptr_t off, target_ulong addr, uintptr_t ra) \
>> +{ \
>> + TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \
>> + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \
>> +}
>
> So in these functions is 'za' pre-adjusted to the start address of the
> vertical column?
Yes. That's true of all of these routines, and what I compute in get_tile_colrow.
> Is 'off' a byte offset here
Yes.
> (in which case the arithmetic is wrong for anything except byte columns)
I don't think so in this case. This is all byte arithmetic. Just as for copy_vertical_*,
there are N rows between elements.
Consider a vertical tile slice of uint64_t:
Element 0 is off=0 -> za + row 0.
Element 1 is off=8 -> za + row 8.
>> + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
>> + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
>
> Theoretically we ought to call gen_check_sp_alignment() here
> for rn == 31, but I guess we didn't do that for any of the
> non-base-A64 instructions like SVE either.
Oh yeah. Some day we should make gen_check_sp_alignment do something too.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 20/45] target/arm: Implement SME LD1, ST1
2022-07-05 1:49 ` Richard Henderson
@ 2022-07-05 10:48 ` Peter Maydell
2022-07-05 11:21 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-05 10:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 5 Jul 2022 at 02:49, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/4/22 16:09, Peter Maydell wrote:
> >> +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
> >> +{
> >> + const uint16_t *src = vsrc;
> >> + uint16_t *dst = vdst;
> >> + size_t i;
> >> +
> >> + for (i = 0; i < len / 2; ++i) {
> >> + dst[i * sizeof(ARMVectorReg)] = src[i];
> >
> > Similarly the array index calculation for dst[] here looks wrong.
>
> I don't think so in this case. I'm not mixing indexes and byte offsets like I was above.
>
> Recall that the next vertical tile element is not in the next physical row, but in the Nth
> physical row. Therefore there are always sizeof(ARMVectorReg) elements in the host layout
> between vertical tile elements.
>
> I agree it looks strange.
Ah yes, I see how this works. I wonder if there's some way we
can abstract out this sort of index calculation into a macro
or function so that we can comment what it's doing there and
then all the use-sites are more "obviously correct". Perhaps:
/*
* When considering the ZA storage as an array of elements of
* type T, the index within that array of the Nth element of
* a vertical slice of a tile can be calculated like this,
* regardless of the size of type T. This is because the tiles
* are interleaved, so if type T is size N bytes then row 1 of
* the tile is N rows away from row 0. The division by N to
* convert a byte offset into an array index and the multiplication
* by N to convert from vslice-index-within-the-tile to
* the index within the ZA storage cancel out.
*/
#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg))
/*
* When doing byte arithmetic on the ZA storage, the element
* byteoff bytes away in a tile vertical slice is always this
* many bytes away in the ZA storage, regardless of the
* size of the tile element, assuming that byteoff is a multiple
* of the element size. Again this is because of the interleaving
* of the tiles. For instance if we have 1 byte per element then
* each row of the ZA storage has one byte of the vslice data,
* and (counting from 0) byte 8 goes in row 8 of the storage
* at offset (8 * row-size-in-bytes).
* If we have 8 bytes per element then each row of the ZA storage
* has 8 bytes of the data, but there are 8 interleaved tiles and
* so byte 8 of the data goes into row 1 of the tile,
* which is again row 8 of the storage, so the offset is still
* (8 * row-size-in-bytes). Similarly for other element sizes.
*/
#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg))
(or use functions if you like. Maybe we want versions that
take (row,col) arguments too.)
Even though we're just multiplying by sizeof(ARMVectorReg)
in both cases it feels to me like having the calculation behind a
function or macro named to indicate whether we're doing byte or
index arithmetic should help make the callsites clearer, and the
reader then only has to convince themselves about the implementations
once.
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 20/45] target/arm: Implement SME LD1, ST1
2022-07-05 10:48 ` Peter Maydell
@ 2022-07-05 11:21 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 11:21 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/5/22 16:18, Peter Maydell wrote:
> Ah yes, I see how this works. I wonder if there's some way we
> can abstract out this sort of index calculation into a macro
> or function so that we can comment what it's doing there and
> then all the use-sites are more "obviously correct". Perhaps:
>
> /*
> * When considering the ZA storage as an array of elements of
> * type T, the index within that array of the Nth element of
> * a vertical slice of a tile can be calculated like this,
> * regardless of the size of type T. This is because the tiles
> * are interleaved, so if type T is size N bytes then row 1 of
> * the tile is N rows away from row 0. The division by N to
> * convert a byte offset into an array index and the multiplication
> * by N to convert from vslice-index-within-the-tile to
> * the index within the ZA storage cancel out.
> */
> #define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg))
>
> /*
> * When doing byte arithmetic on the ZA storage, the element
> * byteoff bytes away in a tile vertical slice is always this
> * many bytes away in the ZA storage, regardless of the
> * size of the tile element, assuming that byteoff is a multiple
> * of the element size. Again this is because of the interleaving
> * of the tiles. For instance if we have 1 byte per element then
> * each row of the ZA storage has one byte of the vslice data,
> * and (counting from 0) byte 8 goes in row 8 of the storage
> * at offset (8 * row-size-in-bytes).
> * If we have 8 bytes per element then each row of the ZA storage
> * has 8 bytes of the data, but there are 8 interleaved tiles and
> * so byte 8 of the data goes into row 1 of the tile,
> * which is again row 8 of the storage, so the offset is still
> * (8 * row-size-in-bytes). Similarly for other element sizes.
> */
> #define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg))
>
> (or use functions if you like. Maybe we want versions that
> take (row,col) arguments too.)
That seems reasonable. I'll work this into v5.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (19 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 20/45] target/arm: Implement SME LD1, ST1 Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 22/45] target/arm: Implement SME LDR, STR Richard Henderson
` (24 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.h | 3 +++
target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++----------
2 files changed, 39 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 2a7fe6e9e7..ad3762d1ac 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -195,4 +195,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, int64_t shift,
uint32_t opr_sz, uint32_t max_sz);
+void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+
#endif /* TARGET_ARM_TRANSLATE_A64_H */
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9e304f78bc..374a0a87f2 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4306,7 +4306,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
* The load should begin at the address Rn + IMM.
*/
-static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
+ int len, int rn, int imm)
{
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
@@ -4332,7 +4333,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
t0 = tcg_temp_new_i64();
for (i = 0; i < len_align; i += 8) {
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ);
- tcg_gen_st_i64(t0, cpu_env, vofs + i);
+ tcg_gen_st_i64(t0, base, vofs + i);
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
tcg_temp_free_i64(t0);
@@ -4345,6 +4346,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);
+ if (base != cpu_env) {
+ TCGv_ptr b = tcg_temp_local_new_ptr();
+ tcg_gen_mov_ptr(b, base);
+ base = b;
+ }
+
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -4352,7 +4359,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
tp = tcg_temp_new_ptr();
- tcg_gen_add_ptr(tp, cpu_env, i);
+ tcg_gen_add_ptr(tp, base, i);
tcg_gen_addi_ptr(i, i, 8);
tcg_gen_st_i64(t0, tp, vofs);
tcg_temp_free_ptr(tp);
@@ -4360,6 +4367,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);
+
+ if (base != cpu_env) {
+ tcg_temp_free_ptr(base);
+ assert(len_remain == 0);
+ }
}
/*
@@ -4388,13 +4400,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
default:
g_assert_not_reached();
}
- tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
+ tcg_gen_st_i64(t0, base, vofs + len_align);
tcg_temp_free_i64(t0);
}
}
/* Similarly for stores. */
-static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
+ int len, int rn, int imm)
{
int len_align = QEMU_ALIGN_DOWN(len, 8);
int len_remain = len % 8;
@@ -4420,7 +4433,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
t0 = tcg_temp_new_i64();
for (i = 0; i < len_align; i += 8) {
- tcg_gen_ld_i64(t0, cpu_env, vofs + i);
+ tcg_gen_ld_i64(t0, base, vofs + i);
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ);
tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
@@ -4434,11 +4447,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);
+ if (base != cpu_env) {
+ TCGv_ptr b = tcg_temp_local_new_ptr();
+ tcg_gen_mov_ptr(b, base);
+ base = b;
+ }
+
gen_set_label(loop);
t0 = tcg_temp_new_i64();
tp = tcg_temp_new_ptr();
- tcg_gen_add_ptr(tp, cpu_env, i);
+ tcg_gen_add_ptr(tp, base, i);
tcg_gen_ld_i64(t0, tp, vofs);
tcg_gen_addi_ptr(i, i, 8);
tcg_temp_free_ptr(tp);
@@ -4449,12 +4468,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);
+
+ if (base != cpu_env) {
+ tcg_temp_free_ptr(base);
+ assert(len_remain == 0);
+ }
}
/* Predicate register stores can be any multiple of 2. */
if (len_remain) {
t0 = tcg_temp_new_i64();
- tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
+ tcg_gen_ld_i64(t0, base, vofs + len_align);
switch (len_remain) {
case 2:
@@ -4486,7 +4510,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- do_ldr(s, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4499,7 +4523,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- do_ldr(s, off, size, a->rn, a->imm * size);
+ gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4512,7 +4536,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = vec_full_reg_size(s);
int off = vec_full_reg_offset(s, a->rd);
- do_str(s, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
@@ -4525,7 +4549,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
if (sve_access_check(s)) {
int size = pred_full_reg_size(s);
int off = pred_full_reg_offset(s, a->rd);
- do_str(s, off, size, a->rn, a->imm * size);
+ gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
}
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 22/45] target/arm: Implement SME LDR, STR
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (20 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
` (23 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sme.decode | 7 +++++++
target/arm/translate-sme.c | 24 ++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 900e3f2a07..f1ebd857a5 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
&ldst rs=%mova_rs
LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
&ldst esz=4 rs=%mova_rs
+
+&ldstr rv rn imm
+@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \
+ &ldstr rv=%mova_rs
+
+LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr
+STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index f9846f137f..87bbf9ab7f 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -246,3 +246,27 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
tcg_temp_free_i64(addr);
return true;
}
+
+typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int);
+
+static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
+{
+ int svl = streaming_vec_reg_size(s);
+ int imm = a->imm;
+ TCGv_ptr base;
+
+ if (!sme_za_enabled_check(s)) {
+ return true;
+ }
+
+ /* ZA[n] equates to ZA0H.B[n]. */
+ base = get_tile_rowcol(s, MO_8, a->rv, imm, false);
+
+ fn(s, base, 0, svl, a->rn, imm * svl);
+
+ tcg_temp_free_ptr(base);
+ return true;
+}
+
+TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
+TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (21 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 22/45] target/arm: Implement SME LDR, STR Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-07-04 10:50 ` Peter Maydell
2022-06-28 4:20 ` [PATCH v4 24/45] target/arm: Implement FMOPA, FMOPS (non-widening) Richard Henderson
` (22 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v4: Drop restrict.
---
target/arm/helper-sme.h | 5 +++
target/arm/sme.decode | 11 +++++
target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 31 +++++++++++++
4 files changed, 137 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 95f6e88bdd..753e9e624c 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -115,3 +115,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i
DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index f1ebd857a5..8cb6c4053c 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr
STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr
+
+### SME Add Vector to Array
+
+&adda zad zn pm pn
+@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda
+@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda
+
+ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32
+ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32
+ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64
+ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 4ff4e22c2c..61fe9e9dc8 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -808,3 +808,93 @@ DO_ST(q, _be, MO_128)
DO_ST(q, _le, MO_128)
#undef DO_ST
+
+void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
+ uint64_t *pn = vpn, *pm = vpm;
+ uint32_t *zda = vzda, *zn = vzn;
+
+ for (row = 0; row < oprsz; ) {
+ uint64_t pa = pn[row >> 4];
+ do {
+ if (pa & 1) {
+ for (col = 0; col < oprsz; ) {
+ uint64_t pb = pm[col >> 4];
+ do {
+ if (pb & 1) {
+ zda[row * sizeof(ARMVectorReg) + col] += zn[col];
+ }
+ pb >>= 4;
+ } while (++col & 15);
+ }
+ }
+ pa >>= 4;
+ } while (++row & 15);
+ }
+}
+
+void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
+ uint8_t *pn = vpn, *pm = vpm;
+ uint64_t *zda = vzda, *zn = vzn;
+
+ for (row = 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ for (col = 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ zda[row * sizeof(ARMVectorReg) + col] += zn[col];
+ }
+ }
+ }
+ }
+}
+
+void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
+ uint64_t *pn = vpn, *pm = vpm;
+ uint32_t *zda = vzda, *zn = vzn;
+
+ for (row = 0; row < oprsz; ) {
+ uint64_t pa = pn[row >> 4];
+ do {
+ if (pa & 1) {
+ uint32_t zn_row = zn[row];
+ for (col = 0; col < oprsz; ) {
+ uint64_t pb = pm[col >> 4];
+ do {
+ if (pb & 1) {
+ zda[row * sizeof(ARMVectorReg) + col] += zn_row;
+ }
+ pb >>= 4;
+ } while (++col & 15);
+ }
+ }
+ pa >>= 4;
+ } while (++row & 15);
+ }
+}
+
+void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
+ uint8_t *pn = vpn, *pm = vpm;
+ uint64_t *zda = vzda, *zn = vzn;
+
+ for (row = 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ uint64_t zn_row = zn[row];
+ for (col = 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ zda[row * sizeof(ARMVectorReg) + col] += zn_row;
+ }
+ }
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 87bbf9ab7f..12995d6a46 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -270,3 +270,34 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
+
+static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
+ gen_helper_gvec_4 *fn)
+{
+ int svl = streaming_vec_reg_size(s);
+ uint32_t desc = simd_desc(svl, svl, 0);
+ TCGv_ptr za, zn, pn, pm;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za = get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn = vec_full_reg_ptr(s, a->zn);
+ pn = pred_full_reg_ptr(s, a->pn);
+ pm = pred_full_reg_ptr(s, a->pm);
+
+ fn(za, zn, pn, pm, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ return true;
+}
+
+TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s)
+TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
+TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
+TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA
2022-06-28 4:20 ` [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
@ 2022-07-04 10:50 ` Peter Maydell
2022-07-05 2:05 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 10:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v4: Drop restrict.
> ---
> target/arm/helper-sme.h | 5 +++
> target/arm/sme.decode | 11 +++++
> target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++
> target/arm/translate-sme.c | 31 +++++++++++++
> 4 files changed, 137 insertions(+)
> #undef DO_ST
> +
> +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn,
> + void *vpm, uint32_t desc)
> +{
> + intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
> + uint64_t *pn = vpn, *pm = vpm;
> + uint32_t *zda = vzda, *zn = vzn;
> +
> + for (row = 0; row < oprsz; ) {
> + uint64_t pa = pn[row >> 4];
> + do {
> + if (pa & 1) {
> + for (col = 0; col < oprsz; ) {
> + uint64_t pb = pm[col >> 4];
> + do {
> + if (pb & 1) {
> + zda[row * sizeof(ARMVectorReg) + col] += zn[col];
> + }
> + pb >>= 4;
> + } while (++col & 15);
> + }
> + }
> + pa >>= 4;
> + } while (++row & 15);
> + }
> +}
> +
> +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
> + void *vpm, uint32_t desc)
> +{
> + intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
> + uint8_t *pn = vpn, *pm = vpm;
> + uint64_t *zda = vzda, *zn = vzn;
> +
> + for (row = 0; row < oprsz; ++row) {
> + if (pn[H1(row)] & 1) {
> + for (col = 0; col < oprsz; ++col) {
> + if (pm[H1(col)] & 1) {
> + zda[row * sizeof(ARMVectorReg) + col] += zn[col];
> + }
> + }
> + }
> + }
> +}
These array index calculations look wrong again?
Should be 'row * (sizeof(ARMVectorReg) / 8) + col' or equivalent,
I think.
> +
> +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn,
> + void *vpm, uint32_t desc)
> +{
> + intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
> + uint64_t *pn = vpn, *pm = vpm;
> + uint32_t *zda = vzda, *zn = vzn;
> +
> + for (row = 0; row < oprsz; ) {
> + uint64_t pa = pn[row >> 4];
> + do {
> + if (pa & 1) {
> + uint32_t zn_row = zn[row];
> + for (col = 0; col < oprsz; ) {
> + uint64_t pb = pm[col >> 4];
> + do {
> + if (pb & 1) {
> + zda[row * sizeof(ARMVectorReg) + col] += zn_row;
> + }
> + pb >>= 4;
> + } while (++col & 15);
> + }
> + }
> + pa >>= 4;
> + } while (++row & 15);
> + }
> +}
> +
> +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
> + void *vpm, uint32_t desc)
> +{
> + intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
> + uint8_t *pn = vpn, *pm = vpm;
> + uint64_t *zda = vzda, *zn = vzn;
> +
> + for (row = 0; row < oprsz; ++row) {
> + if (pn[H1(row)] & 1) {
> + uint64_t zn_row = zn[row];
> + for (col = 0; col < oprsz; ++col) {
> + if (pm[H1(col)] & 1) {
> + zda[row * sizeof(ARMVectorReg) + col] += zn_row;
> + }
> + }
> + }
> + }
> +}
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA
2022-07-04 10:50 ` Peter Maydell
@ 2022-07-05 2:05 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 2:05 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 16:20, Peter Maydell wrote:
>> +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
>> + void *vpm, uint32_t desc)
>> +{
>> + intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
>> + uint8_t *pn = vpn, *pm = vpm;
>> + uint64_t *zda = vzda, *zn = vzn;
>> +
>> + for (row = 0; row < oprsz; ++row) {
>> + if (pn[H1(row)] & 1) {
>> + for (col = 0; col < oprsz; ++col) {
>> + if (pm[H1(col)] & 1) {
>> + zda[row * sizeof(ARMVectorReg) + col] += zn[col];
>> + }
>> + }
>> + }
>> + }
>> +}
>
> These array index calculations look wrong again?
> Should be 'row * (sizeof(ARMVectorReg) / 8) + col' or equivalent,
> I think.
The tile rows are N physical rows apart.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (22 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 25/45] target/arm: Implement BFMOPA, BFMOPS Richard Henderson
` (21 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 5 +++
target/arm/sme.decode | 9 ++++++
target/arm/sme_helper.c | 63 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 32 +++++++++++++++++++
4 files changed, 109 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 753e9e624c..f50d0fe1d6 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -120,3 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 8cb6c4053c..ba4774d174 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32
ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32
ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64
ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64
+
+### SME Outer Product
+
+&op zad zn zm pm pn sub:bool
+@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op
+@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op
+
+FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32
+FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 61fe9e9dc8..31c53ad896 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -25,6 +25,7 @@
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "qemu/int128.h"
+#include "fpu/softfloat.h"
#include "vec_internal.h"
#include "sve_ldst_internal.h"
@@ -898,3 +899,65 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
}
}
}
+
+void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_maxsz(desc);
+ uint32_t neg = simd_data(desc) << 31;
+ uint16_t *pn = vpn, *pm = vpm;
+ float_status fpst = *(float_status *)vst;
+
+ set_default_nan_mode(true, &fpst);
+
+ for (row = 0; row < oprsz; ) {
+ uint16_t pa = pn[H2(row >> 4)];
+ do {
+ if (pa & 1) {
+ void *vza_row = vza + row * sizeof(ARMVectorReg);
+ uint32_t n = *(uint32_t *)(vzn + row) ^ neg;
+
+ for (col = 0; col < oprsz; ) {
+ uint16_t pb = pm[H2(col >> 4)];
+ do {
+ if (pb & 1) {
+ uint32_t *a = vza_row + col;
+ uint32_t *m = vzm + col;
+ *a = float32_muladd(n, *m, *a, 0, vst);
+ }
+ col += 4;
+ pb >>= 4;
+ } while (col & 15);
+ }
+ }
+ row += 4;
+ pa >>= 4;
+ } while (row & 15);
+ }
+}
+
+void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
+ uint64_t neg = (uint64_t)simd_data(desc) << 63;
+ uint64_t *za = vza, *zn = vzn, *zm = vzm;
+ uint8_t *pn = vpn, *pm = vpm;
+ float_status fpst = *(float_status *)vst;
+
+ set_default_nan_mode(true, &fpst);
+
+ for (row = 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ uint64_t *za_row = &za[row * sizeof(ARMVectorReg)];
+ uint64_t n = zn[row] ^ neg;
+
+ for (col = 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ uint64_t *a = &za_row[col];
+ *a = float64_muladd(n, zm[col], *a, 0, &fpst);
+ }
+ }
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 12995d6a46..1117a61f62 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -301,3 +301,35 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s)
TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
+
+static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
+ gen_helper_gvec_5_ptr *fn)
+{
+ int svl = streaming_vec_reg_size(s);
+ uint32_t desc = simd_desc(svl, svl, a->sub);
+ TCGv_ptr za, zn, zm, pn, pm, fpst;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za = get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn = vec_full_reg_ptr(s, a->zn);
+ zm = vec_full_reg_ptr(s, a->zm);
+ pn = pred_full_reg_ptr(s, a->pn);
+ pm = pred_full_reg_ptr(s, a->pm);
+ fpst = fpstatus_ptr(FPST_FPCR);
+
+ fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
+TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 25/45] target/arm: Implement BFMOPA, BFMOPS
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (23 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 24/45] target/arm: Implement FMOPA, FMOPS (non-widening) Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 26/45] target/arm: Implement FMOPA, FMOPS (widening) Richard Henderson
` (20 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c | 52 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 30 ++++++++++++++++++++++
4 files changed, 86 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index f50d0fe1d6..1d68fb8c74 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index ba4774d174..afd9c0dffd 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64
FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32
FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
+
+BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 31c53ad896..d2e1057124 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -961,3 +961,55 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
}
}
}
+
+/*
+ * Alter PAIR as needed for controlling predicates being false,
+ * and for NEG on an enabled row element.
+ */
+static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
+{
+ pair ^= neg;
+ if (!(pg & 1)) {
+ pair &= 0xffff0000u;
+ }
+ if (!(pg & 4)) {
+ pair &= 0x0000ffffu;
+ }
+ return pair;
+}
+
+void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_maxsz(desc);
+ uint32_t neg = simd_data(desc) << 15;
+ uint16_t *pn = vpn, *pm = vpm;
+
+ for (row = 0; row < oprsz; ) {
+ uint16_t pa = pn[H2(row >> 4)];
+ do {
+ void *vza_row = vza + row * sizeof(ARMVectorReg);
+ uint32_t n = *(uint32_t *)(vzn + row);
+
+ n = f16mop_adj_pair(n, pa, neg);
+
+ for (col = 0; col < oprsz; ) {
+ uint16_t pb = pm[H2(col >> 4)];
+ do {
+ if ((pa & 0b0101) == 0b0101 || (pb & 0b0101) == 0b0101) {
+ uint32_t *a = vza_row + col;
+ uint32_t m = *(uint32_t *)(vzm + col);
+
+ m = f16mop_adj_pair(m, pb, neg);
+ *a = bfdotadd(*a, n, m);
+
+ col += 4;
+ pb >>= 4;
+ }
+ } while (col & 15);
+ }
+ row += 4;
+ pa >>= 4;
+ } while (row & 15);
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 1117a61f62..e537a14b6d 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -302,6 +302,33 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
+static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
+ gen_helper_gvec_5 *fn)
+{
+ int svl = streaming_vec_reg_size(s);
+ uint32_t desc = simd_desc(svl, svl, a->sub);
+ TCGv_ptr za, zn, zm, pn, pm;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za = get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn = vec_full_reg_ptr(s, a->zn);
+ zm = vec_full_reg_ptr(s, a->zm);
+ pn = pred_full_reg_ptr(s, a->pn);
+ pm = pred_full_reg_ptr(s, a->pm);
+
+ fn(za, zn, zm, pn, pm, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ return true;
+}
+
static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
gen_helper_gvec_5_ptr *fn)
{
@@ -333,3 +360,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
+
+/* TODO: FEAT_EBF16 */
+TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 26/45] target/arm: Implement FMOPA, FMOPS (widening)
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (24 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 25/45] target/arm: Implement BFMOPA, BFMOPS Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:20 ` [PATCH v4 27/45] target/arm: Implement SME integer outer product Richard Henderson
` (19 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 1 +
target/arm/sme_helper.c | 68 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 1 +
4 files changed, 72 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 1d68fb8c74..4d5d05db3a 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index afd9c0dffd..e8d27fd8a0 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32
FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
+FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index d2e1057124..39d630a91c 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -978,6 +978,74 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
return pair;
}
+static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,
+ float_status *s_std, float_status *s_odd)
+{
+ float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std);
+ float64 e1c = float16_to_float64(e1 >> 16, true, s_std);
+ float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std);
+ float64 e2c = float16_to_float64(e2 >> 16, true, s_std);
+ float64 t64;
+ float32 t32;
+
+ /*
+ * The ARM pseudocode function FPDot performs both multiplies
+ * and the add with a single rounding operation. Emulate this
+ * by performing the first multiply in round-to-odd, then doing
+ * the second multiply as fused multiply-add, and rounding to
+ * float32 all in one step.
+ */
+ t64 = float64_mul(e1r, e2r, s_odd);
+ t64 = float64r32_muladd(e1c, e2c, t64, 0, s_std);
+
+ /* This conversion is exact, because we've already rounded. */
+ t32 = float64_to_float32(t64, s_std);
+
+ /* The final accumulation step is not fused. */
+ return float32_add(sum, t32, s_std);
+}
+
+void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz = simd_maxsz(desc);
+ uint32_t neg = simd_data(desc) << 15;
+ uint16_t *pn = vpn, *pm = vpm;
+ float_status fpst_odd, fpst_std = *(float_status *)vst;
+
+ set_default_nan_mode(true, &fpst_std);
+ fpst_odd = fpst_std;
+ set_float_rounding_mode(float_round_to_odd, &fpst_odd);
+
+ for (row = 0; row < oprsz; ) {
+ uint16_t pa = pn[H2(row >> 4)];
+ do {
+ void *vza_row = vza + row * sizeof(ARMVectorReg);
+ uint32_t n = *(uint32_t *)(vzn + row);
+
+ n = f16mop_adj_pair(n, pa, neg);
+
+ for (col = 0; col < oprsz; ) {
+ uint16_t pb = pm[H2(col >> 4)];
+ do {
+ if ((pa & 0b0101) == 0b0101 || (pb & 0b0101) == 0b0101) {
+ uint32_t *a = vza_row + col;
+ uint32_t m = *(uint32_t *)(vzm + col);
+
+ m = f16mop_adj_pair(m, pb, neg);
+ *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
+
+ col += 4;
+ pb >>= 4;
+ }
+ } while (col & 15);
+ }
+ row += 4;
+ pa >>= 4;
+ } while (row & 15);
+ }
+}
+
void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
void *vpm, uint32_t desc)
{
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index e537a14b6d..0fcb33cb3f 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -358,6 +358,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
return true;
}
+TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_h)
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 27/45] target/arm: Implement SME integer outer product
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (25 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 26/45] target/arm: Implement FMOPA, FMOPS (widening) Richard Henderson
@ 2022-06-28 4:20 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 28/45] target/arm: Implement PSEL Richard Henderson
` (18 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:20 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sme.h | 16 ++++++++
target/arm/sme.decode | 10 +++++
target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 10 +++++
4 files changed, 118 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 4d5d05db3a..d2d544a696 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -129,3 +129,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index e8d27fd8a0..628804e37a 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32
+
+SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32
+SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32
+USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32
+UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32
+
+SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64
+SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64
+USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64
+UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 39d630a91c..e6204ab236 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -1081,3 +1081,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
} while (row & 15);
}
}
+
+typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
+
+static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
+ uint8_t *pn, uint8_t *pm,
+ uint32_t desc, IMOPFn *fn)
+{
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
+ bool neg = simd_data(desc);
+
+ for (row = 0; row < oprsz; ++row) {
+ uint8_t pa = pn[H1(row)];
+ uint64_t *za_row = &za[row * sizeof(ARMVectorReg)];
+ uint64_t n = zn[row];
+
+ for (col = 0; col < oprsz; ++col) {
+ uint8_t pb = pm[H1(col)];
+ uint64_t *a = &za_row[col];
+
+ *a = fn(n, zm[col], *a, pa & pb, neg);
+ }
+ }
+}
+
+#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
+{ \
+ uint32_t sum0 = 0, sum1 = 0; \
+ /* Apply P to N as a mask, making the inactive elements 0. */ \
+ n &= expand_pred_b(p); \
+ sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
+ sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
+ sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
+ sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
+ sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
+ sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
+ sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
+ sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
+ if (neg) { \
+ sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
+ } else { \
+ sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
+ } \
+ return ((uint64_t)sum1 << 32) | sum0; \
+}
+
+#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
+{ \
+ uint64_t sum = 0; \
+ /* Apply P to N as a mask, making the inactive elements 0. */ \
+ n &= expand_pred_h(p); \
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
+ sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
+ sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
+ return neg ? a - sum : a + sum; \
+}
+
+DEF_IMOP_32(smopa_s, int8_t, int8_t)
+DEF_IMOP_32(umopa_s, uint8_t, uint8_t)
+DEF_IMOP_32(sumopa_s, int8_t, uint8_t)
+DEF_IMOP_32(usmopa_s, uint8_t, int8_t)
+
+DEF_IMOP_64(smopa_d, int16_t, int16_t)
+DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
+DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
+DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
+
+#define DEF_IMOPH(NAME) \
+ void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
+ void *vpm, uint32_t desc) \
+ { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
+
+DEF_IMOPH(smopa_s)
+DEF_IMOPH(umopa_s)
+DEF_IMOPH(sumopa_s)
+DEF_IMOPH(usmopa_s)
+DEF_IMOPH(smopa_d)
+DEF_IMOPH(umopa_d)
+DEF_IMOPH(sumopa_d)
+DEF_IMOPH(usmopa_d)
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 0fcb33cb3f..876184e8bd 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -364,3 +364,13 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_f
/* TODO: FEAT_EBF16 */
TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
+
+TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s)
+TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s)
+TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa_s)
+TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa_s)
+
+TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_smopa_d)
+TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_umopa_d)
+TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_sumopa_d)
+TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_usmopa_d)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 28/45] target/arm: Implement PSEL
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (26 preceding siblings ...)
2022-06-28 4:20 ` [PATCH v4 27/45] target/arm: Implement SME integer outer product Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 29/45] target/arm: Implement REVD Richard Henderson
` (17 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 20 +++++++++++++
target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 95af08c139..966803cbb7 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2
### SVE2 floating-point bfloat16 dot-product (indexed)
BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2
+
+### SVE broadcast predicate element
+
+&psel esz pd pn pm rv imm
+%psel_rv 16:2 !function=plus_12
+%psel_imm_b 22:2 19:2
+%psel_imm_h 22:2 20:1
+%psel_imm_s 22:2
+%psel_imm_d 23:1
+@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \
+ &psel rv=%psel_rv
+
+PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \
+ @psel esz=0 imm=%psel_imm_b
+PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \
+ @psel esz=1 imm=%psel_imm_h
+PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \
+ @psel esz=2 imm=%psel_imm_s
+PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
+ @psel esz=3 imm=%psel_imm_d
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 374a0a87f2..23b051746c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7415,3 +7415,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
+
+static bool trans_PSEL(DisasContext *s, arg_psel *a)
+{
+ int vl = vec_full_reg_size(s);
+ int pl = pred_gvec_reg_size(s);
+ int elements = vl >> a->esz;
+ TCGv_i64 tmp, didx, dbit;
+ TCGv_ptr ptr;
+
+ if (!dc_isar_feature(aa64_sme, s)) {
+ return false;
+ }
+ if (!sve_access_check(s)) {
+ return true;
+ }
+
+ tmp = tcg_temp_new_i64();
+ dbit = tcg_temp_new_i64();
+ didx = tcg_temp_new_i64();
+ ptr = tcg_temp_new_ptr();
+
+ /* Compute the predicate element. */
+ tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm);
+ if (is_power_of_2(elements)) {
+ tcg_gen_andi_i64(tmp, tmp, elements - 1);
+ } else {
+ tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements));
+ }
+
+ /* Extract the predicate byte and bit indices. */
+ tcg_gen_shli_i64(tmp, tmp, a->esz);
+ tcg_gen_andi_i64(dbit, tmp, 7);
+ tcg_gen_shri_i64(didx, tmp, 3);
+ if (HOST_BIG_ENDIAN) {
+ tcg_gen_xori_i64(didx, didx, 7);
+ }
+
+ /* Load the predicate word. */
+ tcg_gen_trunc_i64_ptr(ptr, didx);
+ tcg_gen_add_ptr(ptr, ptr, cpu_env);
+ tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
+
+ /* Extract the predicate bit and replicate to MO_64. */
+ tcg_gen_shr_i64(tmp, tmp, dbit);
+ tcg_gen_andi_i64(tmp, tmp, 1);
+ tcg_gen_neg_i64(tmp, tmp);
+
+ /* Apply to either copy the source, or write zeros. */
+ tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd),
+ pred_full_reg_offset(s, a->pn), tmp, pl, pl);
+
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(dbit);
+ tcg_temp_free_i64(didx);
+ tcg_temp_free_ptr(ptr);
+ return true;
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 29/45] target/arm: Implement REVD
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (27 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 28/45] target/arm: Implement PSEL Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP Richard Henderson
` (16 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 2 ++
target/arm/sve.decode | 1 +
target/arm/sve_helper.c | 16 ++++++++++++++++
target/arm/translate-sve.c | 2 ++
4 files changed, 21 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index ab0333400f..cc4e1d8948 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 966803cbb7..a9e48f07b4 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
+REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0
# SVE vector splice (predicated, destructive)
SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 9a26f253e0..5de82696b5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64)
DO_ZPZ_D(sve_revw_d, uint64_t, wswap64)
+void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn;
+ uint8_t *pg = vg;
+
+ for (i = 0; i < opr_sz; i += 2) {
+ if (pg[H1(i)] & 1) {
+ uint64_t n0 = n[i + 0];
+ uint64_t n1 = n[i + 1];
+ d[i + 0] = n1;
+ d[i + 1] = n0;
+ }
+ }
+}
+
DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8)
DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16)
DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 23b051746c..6019dfb53c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2901,6 +2901,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
+TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0)
+
TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
gen_helper_sve_splice, a, a->esz)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (28 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 29/45] target/arm: Implement REVD Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries Richard Henderson
` (15 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 18 +++++++
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++
target/arm/vec_helper.c | 24 +++++++++
4 files changed, 149 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 3a8ce42ab0..92f36d9dbb 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9e48f07b4..14b3a69c36 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \
@psel esz=2 imm=%psel_imm_s
PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
@psel esz=3 imm=%psel_imm_d
+
+### SVE clamp
+
+SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm
+UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 6019dfb53c..2eb9844cda 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7474,3 +7474,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
tcg_temp_free_ptr(ptr);
return true;
}
+
+static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_smax_i32(d, a, n);
+ tcg_gen_smin_i32(d, d, m);
+}
+
+static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_smax_i64(d, a, n);
+ tcg_gen_smin_i64(d, d, m);
+}
+
+static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_smax_vec(vece, d, a, n);
+ tcg_gen_smin_vec(vece, d, d, m);
+}
+
+static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] = {
+ INDEX_op_smin_vec, INDEX_op_smax_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ { .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_b,
+ .opt_opc = vecop,
+ .vece = MO_8 },
+ { .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_h,
+ .opt_opc = vecop,
+ .vece = MO_16 },
+ { .fni4 = gen_sclamp_i32,
+ .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_s,
+ .opt_opc = vecop,
+ .vece = MO_32 },
+ { .fni8 = gen_sclamp_i64,
+ .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_d,
+ .opt_opc = vecop,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a)
+
+static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_umax_i32(d, a, n);
+ tcg_gen_umin_i32(d, d, m);
+}
+
+static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_umax_i64(d, a, n);
+ tcg_gen_umin_i64(d, d, m);
+}
+
+static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_umax_vec(vece, d, a, n);
+ tcg_gen_umin_vec(vece, d, d, m);
+}
+
+static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] = {
+ INDEX_op_umin_vec, INDEX_op_umax_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ { .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_b,
+ .opt_opc = vecop,
+ .vece = MO_8 },
+ { .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_h,
+ .opt_opc = vecop,
+ .vece = MO_16 },
+ { .fni4 = gen_uclamp_i32,
+ .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_s,
+ .opt_opc = vecop,
+ .vece = MO_32 },
+ { .fni8 = gen_uclamp_i64,
+ .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_d,
+ .opt_opc = vecop,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 9a9c034e36..f59d3b26ea 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+#define DO_CLAMP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
+ TYPE aa = *(TYPE *)(a + i); \
+ TYPE nn = *(TYPE *)(n + i); \
+ TYPE mm = *(TYPE *)(m + i); \
+ TYPE dd = MIN(MAX(aa, nn), mm); \
+ *(TYPE *)(d + i) = dd; \
+ } \
+ clear_tail(d, opr_sz, simd_maxsz(desc)); \
+}
+
+DO_CLAMP(gvec_sclamp_b, int8_t)
+DO_CLAMP(gvec_sclamp_h, int16_t)
+DO_CLAMP(gvec_sclamp_s, int32_t)
+DO_CLAMP(gvec_sclamp_d, int64_t)
+
+DO_CLAMP(gvec_uclamp_b, uint8_t)
+DO_CLAMP(gvec_uclamp_h, uint16_t)
+DO_CLAMP(gvec_uclamp_s, uint32_t)
+DO_CLAMP(gvec_uclamp_d, uint64_t)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (29 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 32/45] target/arm: Enable SME for -cpu max Richard Henderson
` (14 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 976e414eda..2dc1f95c6d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11754,6 +11754,19 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
return;
}
+ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+ new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+
+ /*
+ * Both AArch64.TakeException and AArch64.ExceptionReturn
+ * invoke ResetSVEState when taking an exception from, or
+ * returning to, AArch32 state when PSTATE.SM is enabled.
+ */
+ if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) {
+ arm_reset_sve_state(env);
+ return;
+ }
+
/*
* DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
* at ELx, or not available because the EL is in AArch32 state, then
@@ -11766,10 +11779,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
* we already have the correct register contents when encountering the
* vq0->vq0 transition between EL0->EL1.
*/
- old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
old_len = (old_a64 && !sve_exception_el(env, old_el)
? sve_vqm1_for_el(env, old_el) : 0);
- new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
new_len = (new_a64 && !sve_exception_el(env, new_el)
? sve_vqm1_for_el(env, new_el) : 0);
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 32/45] target/arm: Enable SME for -cpu max
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (30 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-06-28 4:21 ` [PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
` (13 subsequent siblings)
45 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Peter Maydell
Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN. This needs to
wait until the kernel ABI is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
docs/system/arm/emulation.rst | 4 ++++
target/arm/cpu64.c | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 83b4410065..8e494c8bea 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -65,6 +65,10 @@ the following architecture extensions:
- FEAT_SHA512 (Advanced SIMD SHA512 instructions)
- FEAT_SM3 (Advanced SIMD SM3 instructions)
- FEAT_SM4 (Advanced SIMD SM4 instructions)
+- FEAT_SME (Scalable Matrix Extension)
+- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
+- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
+- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
- FEAT_SPECRES (Speculation restriction instructions)
- FEAT_SSBS (Speculative Store Bypass Safe)
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 19188d6cc2..40a0f043d0 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1018,6 +1018,7 @@ static void aarch64_max_initfn(Object *obj)
*/
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
+ t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
cpu->isar.id_aa64pfr1 = t;
@@ -1068,6 +1069,16 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
cpu->isar.id_aa64dfr0 = t;
+ t = cpu->isar.id_aa64smfr0;
+ t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
+ cpu->isar.id_aa64smfr0 = t;
+
/* Replicate the same data to the 32-bit id registers. */
aa32_max_features(cpu);
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (31 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 32/45] target/arm: Enable SME for -cpu max Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 11:45 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
` (12 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_cpu.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index 97a477bd3e..f90359faf2 100644
--- a/linux-user/aarch64/target_cpu.h
+++ b/linux-user/aarch64/target_cpu.h
@@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags)
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
- /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
+ /*
+ * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
* different from AArch32 Linux, which uses TPIDRRO.
*/
env->cp15.tpidr_el[0] = newtls;
+ /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */
+ env->cp15.tpidr2_el0 = 0;
}
static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
2022-06-28 4:21 ` [PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
@ 2022-07-04 11:45 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 11:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/target_cpu.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
> index 97a477bd3e..f90359faf2 100644
> --- a/linux-user/aarch64/target_cpu.h
> +++ b/linux-user/aarch64/target_cpu.h
> @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags)
>
> static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
> {
> - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
> + /*
> + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
> * different from AArch32 Linux, which uses TPIDRRO.
> */
> env->cp15.tpidr_el[0] = newtls;
> + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */
> + env->cp15.tpidr2_el0 = 0;
> }
>
> static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (32 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 11:50 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
` (11 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/cpu_loop.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 3b273f6299..4af6996d57 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env)
switch (trapnr) {
case EXCP_SWI:
+ /*
+ * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
+ * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
+ */
+ if (FIELD_EX64(env->svcr, SVCR, SM)) {
+ env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
+ arm_rebuild_hflags(env);
+ arm_reset_sve_state(env);
+ }
ret = do_syscall(env,
env->xregs[8],
env->xregs[0],
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls
2022-06-28 4:21 ` [PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
@ 2022-07-04 11:50 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 11:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 06:26, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/cpu_loop.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
> index 3b273f6299..4af6996d57 100644
> --- a/linux-user/aarch64/cpu_loop.c
> +++ b/linux-user/aarch64/cpu_loop.c
> @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env)
>
> switch (trapnr) {
> case EXCP_SWI:
> + /*
> + * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
> + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
> + */
> + if (FIELD_EX64(env->svcr, SVCR, SM)) {
> + env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
> + arm_rebuild_hflags(env);
> + arm_reset_sve_state(env);
> + }
> ret = do_syscall(env,
> env->xregs[8],
> env->xregs[0],
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (33 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:02 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Richard Henderson
` (10 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Make sure to zero the currently reserved fields.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 7da0e36c6d..3cef2f44cf 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -78,7 +78,8 @@ struct target_extra_context {
struct target_sve_context {
struct target_aarch64_ctx head;
uint16_t vl;
- uint16_t reserved[3];
+ uint16_t flags;
+ uint16_t reserved[2];
/* The actual SVE data immediately follows. It is laid out
* according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
* the original struct pointer.
@@ -101,6 +102,8 @@ struct target_sve_context {
#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
(TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
+#define TARGET_SVE_SIG_FLAG_SM 1
+
struct target_rt_sigframe {
struct target_siginfo info;
struct target_ucontext uc;
@@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_context *sve,
{
int i, j;
+ memset(sve, 0, sizeof(*sve));
__put_user(TARGET_SVE_MAGIC, &sve->head.magic);
__put_user(size, &sve->head.size);
__put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
+ if (FIELD_EX64(env->svcr, SVCR, SM)) {
+ __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
+ }
/* Note that SVE regs are stored as a byte stream, with each byte element
* at a subsequent address. This corresponds to a little-endian store
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context
2022-06-28 4:21 ` [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
@ 2022-07-04 12:02 ` Peter Maydell
2022-07-05 3:24 ` Richard Henderson
0 siblings, 1 reply; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 12:02 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 06:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Make sure to zero the currently reserved fields.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/signal.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
> index 7da0e36c6d..3cef2f44cf 100644
> --- a/linux-user/aarch64/signal.c
> +++ b/linux-user/aarch64/signal.c
> @@ -78,7 +78,8 @@ struct target_extra_context {
> struct target_sve_context {
> struct target_aarch64_ctx head;
> uint16_t vl;
> - uint16_t reserved[3];
> + uint16_t flags;
> + uint16_t reserved[2];
> /* The actual SVE data immediately follows. It is laid out
> * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
> * the original struct pointer.
> @@ -101,6 +102,8 @@ struct target_sve_context {
> #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
> (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
>
> +#define TARGET_SVE_SIG_FLAG_SM 1
> +
> struct target_rt_sigframe {
> struct target_siginfo info;
> struct target_ucontext uc;
> @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_context *sve,
> {
> int i, j;
>
> + memset(sve, 0, sizeof(*sve));
> __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
> __put_user(size, &sve->head.size);
> __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
> + if (FIELD_EX64(env->svcr, SVCR, SM)) {
> + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
> + }
>
The kernel documentation says that if this is set then the SVE
record contains the streaming vector length. Does that happen
automatically (ie vq is the right thing for both streaming
and non-streaming) or do we need to do something there?
I gather that the other half of handling this bit (allowing
it to be changed on signal-return) is in a later patch.
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context
2022-07-04 12:02 ` Peter Maydell
@ 2022-07-05 3:24 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 3:24 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 17:32, Peter Maydell wrote:
>> @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_context *sve,
>> {
>> int i, j;
>>
>> + memset(sve, 0, sizeof(*sve));
>> __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
>> __put_user(size, &sve->head.size);
>> __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
>> + if (FIELD_EX64(env->svcr, SVCR, SM)) {
>> + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
>> + }
>>
>
> The kernel documentation says that if this is set then the SVE
> record contains the streaming vector length. Does that happen
> automatically (ie vq is the right thing for both streaming
> and non-streaming) or do we need to do something there?
It is automatically correct (modulo the typo you found in patch 40). The two helpers we
have are for VL and SVL, with no direct access to NVL.
> I gather that the other half of handling this bit (allowing
> it to be changed on signal-return) is in a later patch.
Yes.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (34 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:04 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
` (9 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Fold the return value setting into the goto, so each
point of failure need not do both.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 3cef2f44cf..8b352abb97 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env,
struct target_sve_context *sve = NULL;
uint64_t extra_datap = 0;
bool used_extra = false;
- bool err = false;
int vq = 0, sve_size = 0;
target_restore_general_frame(env, sf);
@@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env,
switch (magic) {
case 0:
if (size != 0) {
- err = true;
- goto exit;
+ goto err;
}
if (used_extra) {
ctx = NULL;
@@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env,
case TARGET_FPSIMD_MAGIC:
if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
- err = true;
- goto exit;
+ goto err;
}
fpsimd = (struct target_fpsimd_context *)ctx;
break;
@@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env,
break;
}
}
- err = true;
- goto exit;
+ goto err;
case TARGET_EXTRA_MAGIC:
if (extra || size != sizeof(struct target_extra_context)) {
- err = true;
- goto exit;
+ goto err;
}
__get_user(extra_datap,
&((struct target_extra_context *)ctx)->datap);
@@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env,
/* Unknown record -- we certainly didn't generate it.
* Did we in fact get out of sync?
*/
- err = true;
- goto exit;
+ goto err;
}
ctx = (void *)ctx + size;
}
@@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env,
if (fpsimd) {
target_restore_fpsimd_record(env, fpsimd);
} else {
- err = true;
+ goto err;
}
/* SVE data, if present, overwrites FPSIMD data. */
if (sve) {
target_restore_sve_record(env, sve, vq);
}
-
- exit:
unlock_user(extra, extra_datap, 0);
- return err;
+ return 0;
+
+ err:
+ unlock_user(extra, extra_datap, 0);
+ return 1;
}
static abi_ulong get_sigframe(struct target_sigaction *ka,
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (35 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:08 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
` (8 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header. We were silently
allowing these cases to pass, dropping the record.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 8b352abb97..8fbe98d72f 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env,
break;
case TARGET_SVE_MAGIC:
+ if (sve || size < sizeof(struct target_sve_context)) {
+ goto err;
+ }
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
vq = sve_vq(env);
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
- if (!sve && size == sve_size) {
+ if (size == sve_size) {
sve = (struct target_sve_context *)ctx;
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
2022-06-28 4:21 ` [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
@ 2022-07-04 12:08 ` Peter Maydell
2022-07-05 3:27 ` Richard Henderson
2022-07-05 3:30 ` Richard Henderson
0 siblings, 2 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 12:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> In parse_user_sigframe, the kernel rejects duplicate sve records,
> or records that are smaller than the header. We were silently
> allowing these cases to pass, dropping the record.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/signal.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
> index 8b352abb97..8fbe98d72f 100644
> --- a/linux-user/aarch64/signal.c
> +++ b/linux-user/aarch64/signal.c
> @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env,
> break;
>
> case TARGET_SVE_MAGIC:
> + if (sve || size < sizeof(struct target_sve_context)) {
> + goto err;
> + }
> if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
> vq = sve_vq(env);
> sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
> - if (!sve && size == sve_size) {
> + if (size == sve_size) {
> sve = (struct target_sve_context *)ctx;
> break;
> }
On the other hand, the kernel seems to happily allow records
which are larger than the SVE_SIG_CONTEXT_SIZE, whereas we
ignore the record unless there's an exact size match.
I notice the kernel has a bunch of signal frame test
cases in tools/testing/selftests/arm64/signal/testcases --
do we pass those ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
2022-07-04 12:08 ` Peter Maydell
@ 2022-07-05 3:27 ` Richard Henderson
2022-07-05 3:30 ` Richard Henderson
1 sibling, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 3:27 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 17:38, Peter Maydell wrote:
> I notice the kernel has a bunch of signal frame test
> cases in tools/testing/selftests/arm64/signal/testcases --
> do we pass those ?
Most but not all of them. The ones we don't pass are those for which SVE state has been
discarded across a syscall and so the signal frame record is expected to be missing. I
thought about fixing those, but decided not to do within this series.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* Re: [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
2022-07-04 12:08 ` Peter Maydell
2022-07-05 3:27 ` Richard Henderson
@ 2022-07-05 3:30 ` Richard Henderson
2022-07-05 3:32 ` Richard Henderson
1 sibling, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 3:30 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/4/22 17:38, Peter Maydell wrote:
>> case TARGET_SVE_MAGIC:
>> + if (sve || size < sizeof(struct target_sve_context)) {
>> + goto err;
>> + }
>> if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
>> vq = sve_vq(env);
>> sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
>> - if (!sve && size == sve_size) {
>> + if (size == sve_size) {
>> sve = (struct target_sve_context *)ctx;
>> break;
>> }
>
> On the other hand, the kernel seems to happily allow records
> which are larger than the SVE_SIG_CONTEXT_SIZE, whereas we
> ignore the record unless there's an exact size match.
Yeah, this gets fixed properly in patch 39.
Perhaps I should simply squash this with that?
r~
^ permalink raw reply [flat|nested] 93+ messages in thread* Re: [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
2022-07-05 3:30 ` Richard Henderson
@ 2022-07-05 3:32 ` Richard Henderson
0 siblings, 0 replies; 93+ messages in thread
From: Richard Henderson @ 2022-07-05 3:32 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 7/5/22 09:00, Richard Henderson wrote:
> On 7/4/22 17:38, Peter Maydell wrote:
>>> case TARGET_SVE_MAGIC:
>>> + if (sve || size < sizeof(struct target_sve_context)) {
>>> + goto err;
>>> + }
>>> if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
>>> vq = sve_vq(env);
>>> sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
>>> - if (!sve && size == sve_size) {
>>> + if (size == sve_size) {
>>> sve = (struct target_sve_context *)ctx;
>>> break;
>>> }
>>
>> On the other hand, the kernel seems to happily allow records
>> which are larger than the SVE_SIG_CONTEXT_SIZE, whereas we
>> ignore the record unless there's an exact size match.
>
> Yeah, this gets fixed properly in patch 39.
> Perhaps I should simply squash this with that?
Bah! No, those are two separate checks: the minimum size to contain vq and flags
(target_sve_context) and the minimum size to contain all of the vector data
(TARGET_SVE_SIG_CONTEXT_SIZE).
The latter *is* fixed in patch 39, but this one should stay as-is.
r~
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (36 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:11 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore Richard Henderson
` (7 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 8fbe98d72f..9ff79da4be 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env,
__get_user(extra_size,
&((struct target_extra_context *)ctx)->size);
extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
+ if (!extra) {
+ return 1;
+ }
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded
2022-06-28 4:21 ` [PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
@ 2022-07-04 12:11 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 12:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 06:05, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/signal.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
> index 8fbe98d72f..9ff79da4be 100644
> --- a/linux-user/aarch64/signal.c
> +++ b/linux-user/aarch64/signal.c
> @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env,
> __get_user(extra_size,
> &((struct target_extra_context *)ctx)->size);
> extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
> + if (!extra) {
> + return 1;
> + }
> break;
>
> default:
> --
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (37 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 38/45] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:15 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling Richard Henderson
` (6 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Move the checks out of the parsing loop and into the
restore function. This more closely mirrors the code
structure in the kernel, and is slightly clearer.
Reject rather than silently skip incorrect VL and SVE record sizes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 9ff79da4be..22d0b8b4ec 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState *env,
}
}
-static void target_restore_sve_record(CPUARMState *env,
- struct target_sve_context *sve, int vq)
+static bool target_restore_sve_record(CPUARMState *env,
+ struct target_sve_context *sve,
+ int size)
{
- int i, j;
+ int i, j, vl, vq;
- /* Note that SVE regs are stored as a byte stream, with each byte element
+ if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
+ return false;
+ }
+
+ __get_user(vl, &sve->vl);
+ vq = sve_vq(env);
+
+ /* Reject mismatched VL. */
+ if (vl != vq * TARGET_SVE_VQ_BYTES) {
+ return false;
+ }
+
+ /* Accept empty record -- used to clear PSTATE.SM. */
+ if (size <= sizeof(*sve)) {
+ return true;
+ }
+
+ /* Reject non-empty but incomplete record. */
+ if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
+ return false;
+ }
+
+ /*
+ * Note that SVE regs are stored as a byte stream, with each byte element
* at a subsequent address. This corresponds to a little-endian load
* of our 64-bit hunks.
*/
@@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env,
}
}
}
+ return true;
}
static int target_restore_sigframe(CPUARMState *env,
@@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env,
struct target_sve_context *sve = NULL;
uint64_t extra_datap = 0;
bool used_extra = false;
- int vq = 0, sve_size = 0;
+ int sve_size = 0;
target_restore_general_frame(env, sf);
@@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env,
if (sve || size < sizeof(struct target_sve_context)) {
goto err;
}
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
- vq = sve_vq(env);
- sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
- if (size == sve_size) {
- sve = (struct target_sve_context *)ctx;
- break;
- }
- }
- goto err;
+ sve = (struct target_sve_context *)ctx;
+ sve_size = size;
+ break;
case TARGET_EXTRA_MAGIC:
if (extra || size != sizeof(struct target_extra_context)) {
@@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env,
}
/* SVE data, if present, overwrites FPSIMD data. */
- if (sve) {
- target_restore_sve_record(env, sve, vq);
+ if (sve && !target_restore_sve_record(env, sve, sve_size)) {
+ goto err;
}
unlock_user(extra, extra_datap, 0);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (38 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 13:05 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 41/45] linux-user: Rename sve prctls Richard Henderson
` (5 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/signal.c | 162 +++++++++++++++++++++++++++++++++---
1 file changed, 151 insertions(+), 11 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 22d0b8b4ec..1ad125d3d9 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -104,6 +104,22 @@ struct target_sve_context {
#define TARGET_SVE_SIG_FLAG_SM 1
+#define TARGET_ZA_MAGIC 0x54366345
+
+struct target_za_context {
+ struct target_aarch64_ctx head;
+ uint16_t vl;
+ uint16_t reserved[3];
+ /* The actual ZA data immediately follows. */
+};
+
+#define TARGET_ZA_SIG_REGS_OFFSET \
+ QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
+#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
+ (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
+#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
+ TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
+
struct target_rt_sigframe {
struct target_siginfo info;
struct target_ucontext uc;
@@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch64_ctx *end)
}
static void target_setup_sve_record(struct target_sve_context *sve,
- CPUARMState *env, int vq, int size)
+ CPUARMState *env, int size)
{
- int i, j;
+ int i, j, vq = sme_vq(env);
memset(sve, 0, sizeof(*sve));
__put_user(TARGET_SVE_MAGIC, &sve->head.magic);
@@ -207,6 +223,34 @@ static void target_setup_sve_record(struct target_sve_context *sve,
}
}
+static void target_setup_za_record(struct target_za_context *za,
+ CPUARMState *env, int size)
+{
+ int vq = sme_vq(env);
+ int vl = vq * TARGET_SVE_VQ_BYTES;
+ int i, j;
+
+ memset(za, 0, sizeof(*za));
+ __put_user(TARGET_ZA_MAGIC, &za->head.magic);
+ __put_user(size, &za->head.size);
+ __put_user(vl, &za->vl);
+
+ if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+ return;
+ }
+
+ /*
+ * Note that ZA vectors are stored as a byte stream,
+ * with each byte element at a subsequent address.
+ */
+ for (i = 0; i < vl; ++i) {
+ uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+ for (j = 0; j < vq * 2; ++j) {
+ __put_user_e(env->zarray[i].d[j], z + j, le);
+ }
+ }
+}
+
static void target_restore_general_frame(CPUARMState *env,
struct target_rt_sigframe *sf)
{
@@ -252,16 +296,28 @@ static void target_restore_fpsimd_record(CPUARMState *env,
static bool target_restore_sve_record(CPUARMState *env,
struct target_sve_context *sve,
- int size)
+ int size, int *svcr)
{
- int i, j, vl, vq;
+ int i, j, vl, vq, flags;
+ bool sm;
+ /* ??? Kernel tests SVE && (!sm || SME); suggest (sm ? SME : SVE). */
if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
return false;
}
__get_user(vl, &sve->vl);
- vq = sve_vq(env);
+ __get_user(flags, &sve->flags);
+
+ sm = flags & TARGET_SVE_SIG_FLAG_SM;
+ if (sm) {
+ if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ return false;
+ }
+ vq = sme_vq(env);
+ } else {
+ vq = sve_vq(env);
+ }
/* Reject mismatched VL. */
if (vl != vq * TARGET_SVE_VQ_BYTES) {
@@ -278,6 +334,8 @@ static bool target_restore_sve_record(CPUARMState *env,
return false;
}
+ *svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
+
/*
* Note that SVE regs are stored as a byte stream, with each byte element
* at a subsequent address. This corresponds to a little-endian load
@@ -304,15 +362,57 @@ static bool target_restore_sve_record(CPUARMState *env,
return true;
}
+static bool target_restore_za_record(CPUARMState *env,
+ struct target_za_context *za,
+ int size, int *svcr)
+{
+ int i, j, vl, vq;
+
+ if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ return false;
+ }
+
+ __get_user(vl, &za->vl);
+ vq = sme_vq(env);
+
+ /* Reject mismatched VL. */
+ if (vl != vq * TARGET_SVE_VQ_BYTES) {
+ return false;
+ }
+
+ /* Accept empty record -- used to clear PSTATE.ZA. */
+ if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+ return true;
+ }
+
+ /* Reject non-empty but incomplete record. */
+ if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
+ return false;
+ }
+
+ *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
+
+ for (i = 0; i < vl; ++i) {
+ uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+ for (j = 0; j < vq * 2; ++j) {
+ __get_user_e(env->zarray[i].d[j], z + j, le);
+ }
+ }
+ return true;
+}
+
static int target_restore_sigframe(CPUARMState *env,
struct target_rt_sigframe *sf)
{
struct target_aarch64_ctx *ctx, *extra = NULL;
struct target_fpsimd_context *fpsimd = NULL;
struct target_sve_context *sve = NULL;
+ struct target_za_context *za = NULL;
uint64_t extra_datap = 0;
bool used_extra = false;
int sve_size = 0;
+ int za_size = 0;
+ int svcr = 0;
target_restore_general_frame(env, sf);
@@ -350,6 +450,14 @@ static int target_restore_sigframe(CPUARMState *env,
sve_size = size;
break;
+ case TARGET_ZA_MAGIC:
+ if (za || size < sizeof(struct target_za_context)) {
+ goto err;
+ }
+ za = (struct target_za_context *)ctx;
+ za_size = size;
+ break;
+
case TARGET_EXTRA_MAGIC:
if (extra || size != sizeof(struct target_extra_context)) {
goto err;
@@ -381,9 +489,16 @@ static int target_restore_sigframe(CPUARMState *env,
}
/* SVE data, if present, overwrites FPSIMD data. */
- if (sve && !target_restore_sve_record(env, sve, sve_size)) {
+ if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
goto err;
}
+ if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
+ goto err;
+ }
+ if (env->svcr != svcr) {
+ env->svcr = svcr;
+ arm_rebuild_hflags(env);
+ }
unlock_user(extra, extra_datap, 0);
return 0;
@@ -451,7 +566,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
.total_size = offsetof(struct target_rt_sigframe,
uc.tuc_mcontext.__reserved),
};
- int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0;
+ int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
+ int sve_size = 0, za_size = 0;
struct target_rt_sigframe *frame;
struct target_rt_frame_record *fr;
abi_ulong frame_addr, return_addr;
@@ -461,11 +577,20 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
&layout);
/* SVE state needs saving only if it exists. */
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
- vq = sve_vq(env);
- sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
+ cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
sve_ofs = alloc_sigframe_space(sve_size, &layout);
}
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ /* ZA state needs saving only if it is enabled. */
+ if (FIELD_EX64(env->svcr, SVCR, ZA)) {
+ za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(0));
+ } else {
+ za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
+ }
+ za_ofs = alloc_sigframe_space(za_size, &layout);
+ }
if (layout.extra_ofs) {
/* Reserve space for the extra end marker. The standard end marker
@@ -512,7 +637,10 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
target_setup_end_record((void *)frame + layout.extra_end_ofs);
}
if (sve_ofs) {
- target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size);
+ target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
+ }
+ if (za_ofs) {
+ target_setup_za_record((void *)frame + za_ofs, env, za_size);
}
/* Set up the stack frame for unwinding. */
@@ -536,6 +664,18 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
env->btype = 2;
}
+ /*
+ * Invoke the signal handler with both SM and ZA disabled.
+ * When clearing SM, ResetSVEState, per SMSTOP.
+ */
+ if (FIELD_EX64(env->svcr, SVCR, SM)) {
+ arm_reset_sve_state(env);
+ }
+ if (env->svcr) {
+ env->svcr = 0;
+ arm_rebuild_hflags(env);
+ }
+
if (info) {
tswap_siginfo(&frame->info, info);
env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling
2022-06-28 4:21 ` [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling Richard Henderson
@ 2022-07-04 13:05 ` Peter Maydell
0 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 13:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Set the SM bit in the SVE record on signal delivery, create the ZA record.
> Restore SM and ZA state according to the records present on return.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/signal.c | 162 +++++++++++++++++++++++++++++++++---
> 1 file changed, 151 insertions(+), 11 deletions(-)
>
> diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
> index 22d0b8b4ec..1ad125d3d9 100644
> --- a/linux-user/aarch64/signal.c
> +++ b/linux-user/aarch64/signal.c
> @@ -104,6 +104,22 @@ struct target_sve_context {
>
> #define TARGET_SVE_SIG_FLAG_SM 1
>
> +#define TARGET_ZA_MAGIC 0x54366345
> +
> +struct target_za_context {
> + struct target_aarch64_ctx head;
> + uint16_t vl;
> + uint16_t reserved[3];
> + /* The actual ZA data immediately follows. */
> +};
> +
> +#define TARGET_ZA_SIG_REGS_OFFSET \
> + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
> +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
> + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
> +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
> + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
> +
> struct target_rt_sigframe {
> struct target_siginfo info;
> struct target_ucontext uc;
> @@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch64_ctx *end)
> }
>
> static void target_setup_sve_record(struct target_sve_context *sve,
> - CPUARMState *env, int vq, int size)
> + CPUARMState *env, int size)
> {
> - int i, j;
> + int i, j, vq = sme_vq(env);
Shouldn't this be sve_vq() ?
>
> memset(sve, 0, sizeof(*sve));
> __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
> @@ -207,6 +223,34 @@ static void target_setup_sve_record(struct target_sve_context *sve,
> }
> }
>
> +static void target_setup_za_record(struct target_za_context *za,
> + CPUARMState *env, int size)
> +{
> + int vq = sme_vq(env);
> + int vl = vq * TARGET_SVE_VQ_BYTES;
> + int i, j;
> +
> + memset(za, 0, sizeof(*za));
> + __put_user(TARGET_ZA_MAGIC, &za->head.magic);
> + __put_user(size, &za->head.size);
> + __put_user(vl, &za->vl);
> +
> + if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
> + return;
> + }
I know we always set size in code we control, but it feels
a bit fragile to assume that if the size isn't the "for zero
data" case then it definitely has enough space to put all
the ZA data in it. Maybe we could assert() that the code
below isn't going to overrun size ?
> +
> + /*
> + * Note that ZA vectors are stored as a byte stream,
> + * with each byte element at a subsequent address.
> + */
> + for (i = 0; i < vl; ++i) {
> + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
> + for (j = 0; j < vq * 2; ++j) {
> + __put_user_e(env->zarray[i].d[j], z + j, le);
> + }
> + }
> +}
> +
> static void target_restore_general_frame(CPUARMState *env,
> struct target_rt_sigframe *sf)
> {
> @@ -252,16 +296,28 @@ static void target_restore_fpsimd_record(CPUARMState *env,
>
> static bool target_restore_sve_record(CPUARMState *env,
> struct target_sve_context *sve,
> - int size)
> + int size, int *svcr)
> {
> - int i, j, vl, vq;
> + int i, j, vl, vq, flags;
> + bool sm;
>
> + /* ??? Kernel tests SVE && (!sm || SME); suggest (sm ? SME : SVE). */
This is fixed upstream (hasn't made it into Linus' git tree yet
but will at some point):
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/commit/?id=df07443f477a
so we might as well follow suit.
> if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
> return false;
> }
>
> __get_user(vl, &sve->vl);
> - vq = sve_vq(env);
> + __get_user(flags, &sve->flags);
> +
> + sm = flags & TARGET_SVE_SIG_FLAG_SM;
> + if (sm) {
> + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
> + return false;
> + }
> + vq = sme_vq(env);
> + } else {
> + vq = sve_vq(env);
> + }
>
> /* Reject mismatched VL. */
> if (vl != vq * TARGET_SVE_VQ_BYTES) {
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread
* [PATCH v4 41/45] linux-user: Rename sve prctls
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (39 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:16 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Richard Henderson
` (4 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Add "sve" to the sve prctl functions, to distinguish
them from the coming "sme" prctls with similar names.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_prctl.h | 8 ++++----
linux-user/syscall.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index 1d440ffbea..40481e6663 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -6,7 +6,7 @@
#ifndef AARCH64_TARGET_PRCTL_H
#define AARCH64_TARGET_PRCTL_H
-static abi_long do_prctl_get_vl(CPUArchState *env)
+static abi_long do_prctl_sve_get_vl(CPUArchState *env)
{
ARMCPU *cpu = env_archcpu(env);
if (cpu_isar_feature(aa64_sve, cpu)) {
@@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env)
}
return -TARGET_EINVAL;
}
-#define do_prctl_get_vl do_prctl_get_vl
+#define do_prctl_sve_get_vl do_prctl_sve_get_vl
-static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
+static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
{
/*
* We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
@@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
}
return -TARGET_EINVAL;
}
-#define do_prctl_set_vl do_prctl_set_vl
+#define do_prctl_sve_set_vl do_prctl_sve_set_vl
static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
{
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 669add74c1..cbde82c907 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6362,11 +6362,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
#ifndef do_prctl_set_fp_mode
#define do_prctl_set_fp_mode do_prctl_inval1
#endif
-#ifndef do_prctl_get_vl
-#define do_prctl_get_vl do_prctl_inval0
+#ifndef do_prctl_sve_get_vl
+#define do_prctl_sve_get_vl do_prctl_inval0
#endif
-#ifndef do_prctl_set_vl
-#define do_prctl_set_vl do_prctl_inval1
+#ifndef do_prctl_sve_set_vl
+#define do_prctl_sve_set_vl do_prctl_inval1
#endif
#ifndef do_prctl_reset_keys
#define do_prctl_reset_keys do_prctl_inval1
@@ -6431,9 +6431,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
case PR_SET_FP_MODE:
return do_prctl_set_fp_mode(env, arg2);
case PR_SVE_GET_VL:
- return do_prctl_get_vl(env);
+ return do_prctl_sve_get_vl(env);
case PR_SVE_SET_VL:
- return do_prctl_set_vl(env, arg2);
+ return do_prctl_sve_set_vl(env, arg2);
case PR_PAC_RESET_KEYS:
if (arg3 || arg4 || arg5) {
return -TARGET_EINVAL;
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (40 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 41/45] linux-user: Rename sve prctls Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:20 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present Richard Henderson
` (3 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_prctl.h | 48 +++++++++++++++++++++++++++++++
linux-user/syscall.c | 16 +++++++++++
2 files changed, 64 insertions(+)
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index 40481e6663..f8f8f88992 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env)
{
ARMCPU *cpu = env_archcpu(env);
if (cpu_isar_feature(aa64_sve, cpu)) {
+ /* PSTATE.SM is always unset on syscall entry. */
return sve_vq(env) * 16;
}
return -TARGET_EINVAL;
@@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
&& arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
uint32_t vq, old_vq;
+ /* PSTATE.SM is always unset on syscall entry. */
old_vq = sve_vq(env);
/*
@@ -49,6 +51,52 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
}
#define do_prctl_sve_set_vl do_prctl_sve_set_vl
+static abi_long do_prctl_sme_get_vl(CPUArchState *env)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ if (cpu_isar_feature(aa64_sme, cpu)) {
+ return sme_vq(env) * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_sme_get_vl do_prctl_sme_get_vl
+
+static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2)
+{
+ /*
+ * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT.
+ * Note the kernel definition of sve_vl_valid allows for VQ=512,
+ * i.e. VL=8192, even though the architectural maximum is VQ=16.
+ */
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))
+ && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
+ int vq, old_vq;
+
+ old_vq = sme_vq(env);
+
+ /*
+ * Bound the value of vq, so that we know that it fits into
+ * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared
+ * on syscall entry, we are not modifying the current SVE
+ * vector length.
+ */
+ vq = MAX(arg2 / 16, 1);
+ vq = MIN(vq, 16);
+ env->vfp.smcr_el[1] =
+ FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1);
+ vq = sme_vq(env);
+
+ if (old_vq != vq) {
+ /* PSTATE.ZA state is cleared on any change to VQ. */
+ env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0);
+ arm_rebuild_hflags(env);
+ }
+ return vq * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_sme_set_vl do_prctl_sme_set_vl
+
static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
{
ARMCPU *cpu = env_archcpu(env);
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index cbde82c907..991b85e6b4 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6343,6 +6343,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
#ifndef PR_SET_SYSCALL_USER_DISPATCH
# define PR_SET_SYSCALL_USER_DISPATCH 59
#endif
+#ifndef PR_SME_SET_VL
+# define PR_SME_SET_VL 63
+# define PR_SME_GET_VL 64
+# define PR_SME_VL_LEN_MASK 0xffff
+# define PR_SME_VL_INHERIT (1 << 17)
+#endif
#include "target_prctl.h"
@@ -6383,6 +6389,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
#ifndef do_prctl_set_unalign
#define do_prctl_set_unalign do_prctl_inval1
#endif
+#ifndef do_prctl_sme_get_vl
+#define do_prctl_sme_get_vl do_prctl_inval0
+#endif
+#ifndef do_prctl_sme_set_vl
+#define do_prctl_sme_set_vl do_prctl_inval1
+#endif
static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
abi_long arg3, abi_long arg4, abi_long arg5)
@@ -6434,6 +6446,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
return do_prctl_sve_get_vl(env);
case PR_SVE_SET_VL:
return do_prctl_sve_set_vl(env, arg2);
+ case PR_SME_GET_VL:
+ return do_prctl_sme_get_vl(env);
+ case PR_SME_SET_VL:
+ return do_prctl_sme_set_vl(env, arg2);
case PR_PAC_RESET_KEYS:
if (arg3 || arg4 || arg5) {
return -TARGET_EINVAL;
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (41 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:21 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 44/45] target/arm: Enable SME for user-only Richard Henderson
` (2 subsequent siblings)
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4a35890853..20cb622083 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -204,11 +204,10 @@ static void arm_cpu_reset(DeviceState *dev)
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
CPACR_EL1, FPEN, 3);
- /* and to the SVE instructions */
- env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
- CPACR_EL1, ZEN, 3);
- /* with reasonable vector length */
+ /* and to the SVE instructions, with default vector length */
if (cpu_isar_feature(aa64_sve, cpu)) {
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+ CPACR_EL1, ZEN, 3);
env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 44/45] target/arm: Enable SME for user-only
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (42 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:22 ` Peter Maydell
2022-06-28 4:21 ` [PATCH v4 45/45] linux-user/aarch64: Add SME related hwcap entries Richard Henderson
2022-07-04 13:09 ` [PATCH v4 00/45] target/arm: Scalable Matrix Extension Peter Maydell
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 20cb622083..87d836fb2f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -210,6 +210,17 @@ static void arm_cpu_reset(DeviceState *dev)
CPACR_EL1, ZEN, 3);
env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
}
+ /* and for SME instructions, with default vector length, and TPIDR2 */
+ if (cpu_isar_feature(aa64_sme, cpu)) {
+ env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
+ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+ CPACR_EL1, SMEN, 3);
+ env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
+ if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
+ env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
+ SMCR, FA64, 1);
+ }
+ }
/*
* Enable 48-bit address space (TODO: take reserved_va into account).
* Enable TBI0 but not TBI1.
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* [PATCH v4 45/45] linux-user/aarch64: Add SME related hwcap entries
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (43 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 44/45] target/arm: Enable SME for user-only Richard Henderson
@ 2022-06-28 4:21 ` Richard Henderson
2022-07-04 12:24 ` Peter Maydell
2022-07-04 13:09 ` [PATCH v4 00/45] target/arm: Scalable Matrix Extension Peter Maydell
45 siblings, 1 reply; 93+ messages in thread
From: Richard Henderson @ 2022-06-28 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/elfload.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 163fc8a1ee..a496c37855 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -605,6 +605,18 @@ enum {
ARM_HWCAP2_A64_RNG = 1 << 16,
ARM_HWCAP2_A64_BTI = 1 << 17,
ARM_HWCAP2_A64_MTE = 1 << 18,
+ ARM_HWCAP2_A64_ECV = 1 << 19,
+ ARM_HWCAP2_A64_AFP = 1 << 20,
+ ARM_HWCAP2_A64_RPRES = 1 << 21,
+ ARM_HWCAP2_A64_MTE3 = 1 << 22,
+ ARM_HWCAP2_A64_SME = 1 << 23,
+ ARM_HWCAP2_A64_SME_I16I64 = 1 << 24,
+ ARM_HWCAP2_A64_SME_F64F64 = 1 << 25,
+ ARM_HWCAP2_A64_SME_I8I32 = 1 << 26,
+ ARM_HWCAP2_A64_SME_F16F32 = 1 << 27,
+ ARM_HWCAP2_A64_SME_B16F32 = 1 << 28,
+ ARM_HWCAP2_A64_SME_F32F32 = 1 << 29,
+ ARM_HWCAP2_A64_SME_FA64 = 1 << 30,
};
#define ELF_HWCAP get_elf_hwcap()
@@ -674,6 +686,14 @@ static uint32_t get_elf_hwcap2(void)
GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+ GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME |
+ ARM_HWCAP2_A64_SME_F32F32 |
+ ARM_HWCAP2_A64_SME_B16F32 |
+ ARM_HWCAP2_A64_SME_F16F32 |
+ ARM_HWCAP2_A64_SME_I8I32));
+ GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64);
+ GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64);
+ GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64);
return hwcaps;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 93+ messages in thread* Re: [PATCH v4 00/45] target/arm: Scalable Matrix Extension
2022-06-28 4:20 [PATCH v4 00/45] target/arm: Scalable Matrix Extension Richard Henderson
` (44 preceding siblings ...)
2022-06-28 4:21 ` [PATCH v4 45/45] linux-user/aarch64: Add SME related hwcap entries Richard Henderson
@ 2022-07-04 13:09 ` Peter Maydell
45 siblings, 0 replies; 93+ messages in thread
From: Peter Maydell @ 2022-07-04 13:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Tue, 28 Jun 2022 at 05:21, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Changes for v4:
> * Rebase on mainline (20 patches upstreamed).
> * Adjust sve_access_check when PSTATE.SM set.
> * Adjust sve insns to indicate not valid while streaming.
> * Other misc adjustments per review.
>
Hi; I've reviewed as much of v4 as I'm going to now.
thanks
-- PMM
^ permalink raw reply [flat|nested] 93+ messages in thread