From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F48FC433EF for ; Tue, 28 Jun 2022 04:57:12 +0000 (UTC) Received: from localhost ([::1]:42088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Hj-0005lf-5C for qemu-devel@archiver.kernel.org; Tue, 28 Jun 2022 00:57:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62ni-0000F4-Jk for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:10 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:36598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62ng-0004Nt-9S for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:09 -0400 Received: by mail-pj1-x102f.google.com with SMTP id c6-20020a17090abf0600b001eee794a478so3913707pjs.1 for ; Mon, 27 Jun 2022 21:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XzmAsw+HehUgAR34ijj4idKuyBEWb7euFeYY0G4Evdg=; b=gUGPKIvi4ZWycsTjoR8nwk2UV/r9O8uhCXbDBVxirKqVAPBwE34Pxsvn7s4TZvvUJU 7wsgMD2ZATeXWLH+l+5GNQHbmuQjt/mRz+ilPXVVgHZ9Mu5vNhfVi+MZaNcBowXwmgDD MdhO5VFBLK6A7slOhDRMExECC/9Dp1EauxpwhsYy6K2p7SAcZiPtpoqkNC1PcswtpFV8 LC59T550tYuqQcSuFs32Q0GqP7hz+VccV+sajI4hTROAdf2FFzfhJiOTC0F9jU1EJ8gI F/uJ4VzhwXgCXrgLT2JR/nvpFFfd8LWFOeSJV14wXpFdaLTjPV1JaKaMdIWK1SPEaFvI fPTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XzmAsw+HehUgAR34ijj4idKuyBEWb7euFeYY0G4Evdg=; b=NYci7h+GcvVF4SLBC/idwbyk1qkOB2nuI7/filLhkGr5qvpuqo4uI1wsOEWgCZXZ78 Hgfi3lPLCjeq0TpoQHT0deY9/+wME0cmDAhQ1etClS5DdxUIqhl02EDASJgJfL0ZMZDL kcOQPxedDBNFHAcROEoMjSuQZqGM7LzVnlRD76Y6vcJsxWXTJBNLKzQh4v184VXrjV8B bHeWlpFe+F5FcHD0BGcBND2aQATjtcPHOihhVukKTTNECpvo5I4iaqw5yMAQzCUU35i4 qLYJ3HteWtgT/fpz21SfXmLogYOeqTnnKR4Rlz1Ri0WwO5Q6CYh/3O2Dgzx5aME7Syfc CGMA== X-Gm-Message-State: AJIora+YZg2+9xhquLsm6tfvDJNBjGj3UtRuekveo7VA0K5usreJnh1G 1I711riQUHtLXPcq0XAzPTyLMP/GtW7Ltg== X-Google-Smtp-Source: AGRyM1v0O4ISpFA0dUu244rYwNA4qquLhGpHqyfW0fnQ6T5gpvXqayX9cRRxM136JqtBHrjEdEvnEQ== X-Received: by 2002:a17:90b:4c92:b0:1ec:ea7c:89af with SMTP id my18-20020a17090b4c9200b001ecea7c89afmr25144105pjb.195.1656390366971; Mon, 27 Jun 2022 21:26:06 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Tue, 28 Jun 2022 09:51:14 +0530 Message-Id: <20220628042117.368549-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 40481e6663..f8f8f88992 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; + /* PSTATE.SM is always unset on syscall entry. */ old_vq = sve_vq(env); /* @@ -49,6 +51,52 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq = sme_vq(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, 16); + env->vfp.smcr_el[1] = + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + vq = sme_vq(env); + + if (old_vq != vq) { + /* PSTATE.ZA state is cleared on any change to VQ. */ + env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu = env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index cbde82c907..991b85e6b4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6343,6 +6343,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif #include "target_prctl.h" @@ -6383,6 +6389,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6434,6 +6446,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; -- 2.34.1