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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id bf27-20020a2eaa1b000000b0025911ee8411sm1857972ljb.14.2022.06.28.09.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 09:22:52 -0700 (PDT) Date: Tue, 28 Jun 2022 18:22:50 +0200 From: Francisco Iglesias To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: Iris Chen , pdel@fb.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, patrick@stwcx.xyz, alistair@alistair23.me, kwolf@redhat.com, hreitz@redhat.com, peter.maydell@linaro.org, andrew@aj.id.au, joel@jms.id.au, thuth@redhat.com, lvivier@redhat.com, pbonzini@redhat.com, qemu-block@nongnu.org, dz4list@gmail.com, Iris Chen Subject: Re: [PATCH v4] hw: m25p80: add WP# pin and SRWD bit for write protection Message-ID: <20220628162249.GA10966@fralle-msi> References: <20220621202427.2680413-1-irischenlj@fb.com> <20220622094542.GE10629@fralle-msi> <61a77a3a-ca38-f4d1-8c18-5d240360e0ba@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <61a77a3a-ca38-f4d1-8c18-5d240360e0ba@kaod.org> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On [2022 Jun 28] Tue 17:52:50, Cédric Le Goater wrote: > Alistair, Francisco, > > On 6/22/22 11:45, Francisco Iglesias wrote: > > On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote: > > > From: Iris Chen > > > > > > Signed-off-by: Iris Chen > > > > Reviewed-by: Francisco Iglesias > > I am planning to include this patch in the next aspeed PR if that's > OK with you. Sounds good to me Cédric! Best regards, Francisco > > Thanks, > > C. > > > > > > --- > > > Fixed .needed for subsection and suggestions from Francisco > > > > > > hw/block/m25p80.c | 82 ++++++++++++++++++++++++++++++++++++++--------- > > > 1 file changed, 67 insertions(+), 15 deletions(-) > > > > > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c > > > index 81ba3da4df..3045dda53b 100644 > > > --- a/hw/block/m25p80.c > > > +++ b/hw/block/m25p80.c > > > @@ -472,11 +472,13 @@ struct Flash { > > > uint8_t spansion_cr2v; > > > uint8_t spansion_cr3v; > > > uint8_t spansion_cr4v; > > > + bool wp_level; > > > bool write_enable; > > > bool four_bytes_address_mode; > > > bool reset_enable; > > > bool quad_enable; > > > bool aai_enable; > > > + bool status_register_write_disabled; > > > uint8_t ear; > > > int64_t dirty_page; > > > @@ -723,6 +725,8 @@ static void complete_collecting_data(Flash *s) > > > flash_erase(s, s->cur_addr, s->cmd_in_progress); > > > break; > > > case WRSR: > > > + s->status_register_write_disabled = extract32(s->data[0], 7, 1); > > > + > > > switch (get_man(s)) { > > > case MAN_SPANSION: > > > s->quad_enable = !!(s->data[1] & 0x02); > > > @@ -1165,22 +1169,34 @@ static void decode_new_cmd(Flash *s, uint32_t value) > > > break; > > > case WRSR: > > > - if (s->write_enable) { > > > - switch (get_man(s)) { > > > - case MAN_SPANSION: > > > - s->needed_bytes = 2; > > > - s->state = STATE_COLLECTING_DATA; > > > - break; > > > - case MAN_MACRONIX: > > > - s->needed_bytes = 2; > > > - s->state = STATE_COLLECTING_VAR_LEN_DATA; > > > - break; > > > - default: > > > - s->needed_bytes = 1; > > > - s->state = STATE_COLLECTING_DATA; > > > - } > > > - s->pos = 0; > > > + /* > > > + * If WP# is low and status_register_write_disabled is high, > > > + * status register writes are disabled. > > > + * This is also called "hardware protected mode" (HPM). All other > > > + * combinations of the two states are called "software protected mode" > > > + * (SPM), and status register writes are permitted. > > > + */ > > > + if ((s->wp_level == 0 && s->status_register_write_disabled) > > > + || !s->write_enable) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "M25P80: Status register write is disabled!\n"); > > > + break; > > > + } > > > + > > > + switch (get_man(s)) { > > > + case MAN_SPANSION: > > > + s->needed_bytes = 2; > > > + s->state = STATE_COLLECTING_DATA; > > > + break; > > > + case MAN_MACRONIX: > > > + s->needed_bytes = 2; > > > + s->state = STATE_COLLECTING_VAR_LEN_DATA; > > > + break; > > > + default: > > > + s->needed_bytes = 1; > > > + s->state = STATE_COLLECTING_DATA; > > > } > > > + s->pos = 0; > > > break; > > > case WRDI: > > > @@ -1195,6 +1211,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) > > > case RDSR: > > > s->data[0] = (!!s->write_enable) << 1; > > > + s->data[0] |= (!!s->status_register_write_disabled) << 7; > > > + > > > if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) { > > > s->data[0] |= (!!s->quad_enable) << 6; > > > } > > > @@ -1484,6 +1502,14 @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx) > > > return r; > > > } > > > +static void m25p80_write_protect_pin_irq_handler(void *opaque, int n, int level) > > > +{ > > > + Flash *s = M25P80(opaque); > > > + /* WP# is just a single pin. */ > > > + assert(n == 0); > > > + s->wp_level = !!level; > > > +} > > > + > > > static void m25p80_realize(SSIPeripheral *ss, Error **errp) > > > { > > > Flash *s = M25P80(ss); > > > @@ -1515,12 +1541,18 @@ static void m25p80_realize(SSIPeripheral *ss, Error **errp) > > > s->storage = blk_blockalign(NULL, s->size); > > > memset(s->storage, 0xFF, s->size); > > > } > > > + > > > + qdev_init_gpio_in_named(DEVICE(s), > > > + m25p80_write_protect_pin_irq_handler, "WP#", 1); > > > } > > > static void m25p80_reset(DeviceState *d) > > > { > > > Flash *s = M25P80(d); > > > + s->wp_level = true; > > > + s->status_register_write_disabled = false; > > > + > > > reset_memory(s); > > > } > > > @@ -1587,6 +1619,25 @@ static const VMStateDescription vmstate_m25p80_aai_enable = { > > > } > > > }; > > > +static bool m25p80_wp_level_srwd_needed(void *opaque) > > > +{ > > > + Flash *s = (Flash *)opaque; > > > + > > > + return !s->wp_level || s->status_register_write_disabled; > > > +} > > > + > > > +static const VMStateDescription vmstate_m25p80_write_protect = { > > > + .name = "m25p80/write_protect", > > > + .version_id = 1, > > > + .minimum_version_id = 1, > > > + .needed = m25p80_wp_level_srwd_needed, > > > + .fields = (VMStateField[]) { > > > + VMSTATE_BOOL(wp_level, Flash), > > > + VMSTATE_BOOL(status_register_write_disabled, Flash), > > > + VMSTATE_END_OF_LIST() > > > + } > > > +}; > > > + > > > static const VMStateDescription vmstate_m25p80 = { > > > .name = "m25p80", > > > .version_id = 0, > > > @@ -1618,6 +1669,7 @@ static const VMStateDescription vmstate_m25p80 = { > > > .subsections = (const VMStateDescription * []) { > > > &vmstate_m25p80_data_read_loop, > > > &vmstate_m25p80_aai_enable, > > > + &vmstate_m25p80_write_protect, > > > NULL > > > } > > > }; > > > -- > > > 2.30.2 > > > > > > >