* [PATCH 0/2] target/riscv: Fixes for Ibex and OpenTitan @ 2022-06-29 23:31 Alistair Francis 2022-06-29 23:31 ` [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis 2022-06-29 23:31 ` [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 Alistair Francis 0 siblings, 2 replies; 6+ messages in thread From: Alistair Francis @ 2022-06-29 23:31 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Alistair Francis, Palmer Dabbelt, Bin Meng, alistair23, bmeng.cn From: Alistair Francis <alistair.francis@wdc.com> This fixes some issues discovered on the Ibex SoC when running OpenTitan tests. Alistair Francis (2): target/riscv: Fixup MSECCFG minimum priv check target/riscv: Ibex: Support priv version 1.11 target/riscv/cpu.c | 2 +- target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.36.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check 2022-06-29 23:31 [PATCH 0/2] target/riscv: Fixes for Ibex and OpenTitan Alistair Francis @ 2022-06-29 23:31 ` Alistair Francis 2022-07-01 12:32 ` Bin Meng 2022-06-29 23:31 ` [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 Alistair Francis 1 sibling, 1 reply; 6+ messages in thread From: Alistair Francis @ 2022-06-29 23:31 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Alistair Francis, Palmer Dabbelt, Bin Meng, alistair23, bmeng.cn From: Alistair Francis <alistair.francis@wdc.com> There is nothing in the RISC-V spec that mandates version 1.12 is required for ePMP and there is currently hardware [1] that implements ePMP (a draft version though) with the 1.11 priv spec. 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..6379bef5a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Physical Memory Protection */ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, - .min_priv_ver = PRIV_VERSION_1_12_0 }, + .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, -- 2.36.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check 2022-06-29 23:31 ` [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis @ 2022-07-01 12:32 ` Bin Meng 2022-07-02 6:53 ` Alistair Francis 0 siblings, 1 reply; 6+ messages in thread From: Bin Meng @ 2022-07-01 12:32 UTC (permalink / raw) To: Alistair Francis Cc: open list:RISC-V, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng, Alistair Francis On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.francis@wdc.com> > > There is nothing in the RISC-V spec that mandates version 1.12 is > required for ePMP and there is currently hardware [1] that implements > ePMP (a draft version though) with the 1.11 priv spec. > > 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html > > Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops. The format is Fixes: 12 digits commit id ("commit title") > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6dbe9b541f..6379bef5a5 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > /* Physical Memory Protection */ > [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > + .min_priv_ver = PRIV_VERSION_1_11_0 }, > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, > -- > Other than that, Reviewed-by: Bin Meng <bmeng.cn@gmail.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check 2022-07-01 12:32 ` Bin Meng @ 2022-07-02 6:53 ` Alistair Francis 0 siblings, 0 replies; 6+ messages in thread From: Alistair Francis @ 2022-07-02 6:53 UTC (permalink / raw) To: Bin Meng Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng On Fri, Jul 1, 2022 at 10:32 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis > <alistair.francis@opensource.wdc.com> wrote: > > > > From: Alistair Francis <alistair.francis@wdc.com> > > > > There is nothing in the RISC-V spec that mandates version 1.12 is > > required for ePMP and there is currently hardware [1] that implements > > ePMP (a draft version though) with the 1.11 priv spec. > > > > 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html > > > > Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops. > > The format is > > Fixes: 12 digits commit id ("commit title") Thanks! I meant to come back and fix this up but then forgot Applied to riscv-to-apply.next Alistair > > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > > --- > > target/riscv/csr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6dbe9b541f..6379bef5a5 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > > > /* Physical Memory Protection */ > > [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, > > - .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + .min_priv_ver = PRIV_VERSION_1_11_0 }, > > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, > > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, > > [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, > > -- > > > > Other than that, > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 2022-06-29 23:31 [PATCH 0/2] target/riscv: Fixes for Ibex and OpenTitan Alistair Francis 2022-06-29 23:31 ` [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis @ 2022-06-29 23:31 ` Alistair Francis 2022-07-01 12:32 ` Bin Meng 1 sibling, 1 reply; 6+ messages in thread From: Alistair Francis @ 2022-06-29 23:31 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Alistair Francis, Palmer Dabbelt, Bin Meng, alistair23, bmeng.cn From: Alistair Francis <alistair.francis@wdc.com> The Ibex CPU supports version 1.11 of the priv spec [1], so let's correct that in QEMU as well. 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05e6521351..178b4de51f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -237,7 +237,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; cpu->cfg.epmp = true; } -- 2.36.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 2022-06-29 23:31 ` [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 Alistair Francis @ 2022-07-01 12:32 ` Bin Meng 0 siblings, 0 replies; 6+ messages in thread From: Bin Meng @ 2022-07-01 12:32 UTC (permalink / raw) To: Alistair Francis Cc: open list:RISC-V, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bin Meng, Alistair Francis On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.francis@wdc.com> > > The Ibex CPU supports version 1.11 of the priv spec [1], so let's > correct that in QEMU as well. > > 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-07-02 6:56 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-29 23:31 [PATCH 0/2] target/riscv: Fixes for Ibex and OpenTitan Alistair Francis 2022-06-29 23:31 ` [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis 2022-07-01 12:32 ` Bin Meng 2022-07-02 6:53 ` Alistair Francis 2022-06-29 23:31 ` [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11 Alistair Francis 2022-07-01 12:32 ` Bin Meng
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