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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup
Date: Sun,  3 Jul 2022 13:53:33 +0530	[thread overview]
Message-ID: <20220703082419.770989-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/internals.h | 11 +++++------
 target/arm/m_helper.c  | 16 +++++++---------
 target/arm/ptw.c       | 20 +++++++++-----------
 3 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 7d08917f88..a817acaaf4 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1115,12 +1115,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
                          MMUAccessType access_type, ARMMMUIdx mmu_idx,
                          V8M_SAttributes *sattrs);
 
-bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
-                       MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                       hwaddr *phys_ptr, MemTxAttrs *txattrs,
-                       int *prot, bool *is_subpage,
-                       ARMMMUFaultInfo *fi, uint32_t *mregion);
-
 /* Cacheability and shareability attributes for a memory access */
 typedef struct ARMCacheAttrs {
     /*
@@ -1147,6 +1141,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
                    GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
     __attribute__((nonnull));
 
+bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+                       MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                       GetPhysAddrResult *result, bool *is_subpage,
+                       ARMMMUFaultInfo *fi, uint32_t *mregion);
+
 void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 84c6796b8d..69d4a63fa6 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2770,15 +2770,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     V8M_SAttributes sattrs = {};
     uint32_t tt_resp;
     bool r, rw, nsr, nsrw, mrvalid;
-    int prot;
-    ARMMMUFaultInfo fi = {};
-    MemTxAttrs attrs = {};
-    hwaddr phys_addr;
     ARMMMUIdx mmu_idx;
     uint32_t mregion;
     bool targetpriv;
     bool targetsec = env->v7m.secure;
-    bool is_subpage;
 
     /*
      * Work out what the security state and privilege level we're
@@ -2809,18 +2804,21 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
      * inspecting the other MPU state.
      */
     if (arm_current_el(env) != 0 || alt) {
+        GetPhysAddrResult res = {};
+        ARMMMUFaultInfo fi = {};
+        bool is_subpage;
+
         /* We can ignore the return value as prot is always set */
         pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
-                          &phys_addr, &attrs, &prot, &is_subpage,
-                          &fi, &mregion);
+                          &res, &is_subpage, &fi, &mregion);
         if (mregion == -1) {
             mrvalid = false;
             mregion = 0;
         } else {
             mrvalid = true;
         }
-        r = prot & PAGE_READ;
-        rw = prot & PAGE_WRITE;
+        r = res.prot & PAGE_READ;
+        rw = res.prot & PAGE_WRITE;
     } else {
         r = false;
         rw = false;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ef28258d51..b012577f17 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1697,8 +1697,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
 
 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                        MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                       hwaddr *phys_ptr, MemTxAttrs *txattrs,
-                       int *prot, bool *is_subpage,
+                       GetPhysAddrResult *result, bool *is_subpage,
                        ARMMMUFaultInfo *fi, uint32_t *mregion)
 {
     /*
@@ -1720,8 +1719,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
     uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
 
     *is_subpage = false;
-    *phys_ptr = address;
-    *prot = 0;
+    result->phys = address;
+    result->prot = 0;
     if (mregion) {
         *mregion = -1;
     }
@@ -1803,7 +1802,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
 
     if (matchregion == -1) {
         /* hit using the background region */
-        get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
+        get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
     } else {
         uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
         uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
@@ -1818,9 +1817,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
             xn = 1;
         }
 
-        *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
-        if (*prot && !xn && !(pxn && !is_user)) {
-            *prot |= PAGE_EXEC;
+        result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
+        if (result->prot && !xn && !(pxn && !is_user)) {
+            result->prot |= PAGE_EXEC;
         }
         /*
          * We don't need to look the attribute up in the MAIR0/MAIR1
@@ -1833,7 +1832,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
 
     fi->type = ARMFault_Permission;
     fi->level = 1;
-    return !(*prot & (1 << access_type));
+    return !(result->prot & (1 << access_type));
 }
 
 static bool v8m_is_sau_exempt(CPUARMState *env,
@@ -2032,8 +2031,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
     }
 
     ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx,
-                            &result->phys, &result->attrs, &result->prot,
-                            &mpu_is_subpage, fi, NULL);
+                            result, &mpu_is_subpage, fi, NULL);
     result->page_size =
         sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
     return ret;
-- 
2.34.1



  parent reply	other threads:[~2022-07-03  8:51 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-03  8:23 [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-03  8:23 ` [PATCH 01/62] accel/tcg: Introduce PageEntryExtra Richard Henderson
2022-07-04 15:28   ` Peter Maydell
2022-07-05  0:35     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 02/62] target/arm: Enable PageEntryExtra Richard Henderson
2022-07-04 15:22   ` Peter Maydell
2022-07-05  1:01     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 03/62] target/arm: Fix MTE check in sve_ldnfff1_r Richard Henderson
2022-07-05 12:05   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page Richard Henderson
2022-07-05 12:09   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 05/62] target/arm: Use PageEntryExtra for MTE Richard Henderson
2022-07-05 12:47   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 06/62] target/arm: Use PageEntryExtra for BTI Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 08/62] target/arm: Create GetPhysAddrResult Richard Henderson
2022-08-10 13:02   ` Alex Bennée
2022-08-19 17:31     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` Richard Henderson [this message]
2022-08-10 13:09   ` [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Alex Bennée
2022-07-03  8:23 ` [PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:11   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup Richard Henderson
2022-08-10 13:13   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 22/62] target/arm: Add secure parameter to get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:16   ` Alex Bennée
2022-08-10 15:33     ` Richard Henderson
2022-08-10 18:46       ` Alex Bennée
2022-07-03  8:23 ` [PATCH 23/62] target/arm: Add is_secure parameter to pmsav7_use_background_region Richard Henderson
2022-08-10 13:17   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 24/62] target/arm: Add is_secure parameter to get_phys_addr_lpae Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 25/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 26/62] target/arm: Add is_secure parameter to regime_translation_disabled Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 28/62] target/arm: Split out get_phys_addr_with_secure Richard Henderson
2022-07-03  8:23 ` [PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn Richard Henderson
2022-08-10 13:27   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE Richard Henderson
2022-07-03  8:23 ` [PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write Richard Henderson
2022-07-03  8:23 ` [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes Richard Henderson
2022-07-03  8:23 ` [PATCH 34/62] target/arm: Reorg regime_translation_disabled Richard Henderson
2022-07-03  8:23 ` [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Richard Henderson
2022-07-03  8:23 ` [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate Richard Henderson
2022-07-03  8:23 ` [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate Richard Henderson
2022-07-03  8:23 ` [PATCH 38/62] target/arm: Fix S2 disabled check " Richard Henderson
2022-07-03  8:23 ` [PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb Richard Henderson
2022-07-03  8:23 ` [PATCH 40/62] target/arm: Pass HCR to attribute subroutines Richard Henderson
2022-07-03  8:23 ` [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1 Richard Henderson
2022-07-03  8:23 ` [PATCH 42/62] target/arm: Split out get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} Richard Henderson
2022-07-03  8:24 ` [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Richard Henderson
2022-07-03  8:24 ` [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking Richard Henderson
2022-07-03  8:24 ` [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation Richard Henderson
2022-07-03  8:24 ` [PATCH 48/62] target/arm: Split out get_phys_addr_twostage Richard Henderson
2022-07-03  8:24 ` [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines Richard Henderson
2022-07-03  8:24 ` [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation Richard Henderson
2022-07-03  8:24 ` [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate Richard Henderson
2022-07-03  8:24 ` [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS Richard Henderson
2022-07-03  8:24 ` [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters Richard Henderson
2022-07-03  8:24 ` [PATCH 54/62] target/arm: Split out S1TranslateResult type Richard Henderson
2022-07-03  8:24 ` [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult Richard Henderson
2022-07-03  8:24 ` [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Richard Henderson
2022-07-03  8:24 ` [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate Richard Henderson
2022-07-03  8:24 ` [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 60/62] target/arm: Don't shift attrs " Richard Henderson
2022-07-03  8:24 ` [PATCH 61/62] target/arm: Consider GP an attribute " Richard Henderson
2022-07-03  8:24 ` [PATCH 62/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-04 14:54 ` [PATCH 00/62] " Peter Maydell
2022-07-04 14:58   ` Richard Henderson
2022-07-04 15:57     ` Peter Maydell
2022-08-12 16:31 ` Peter Maydell
2022-08-12 17:54   ` Richard Henderson

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