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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup
Date: Sun,  3 Jul 2022 13:53:35 +0530	[thread overview]
Message-ID: <20220703082419.770989-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org>

Remove the use of regime_is_secure from v8m_security_lookup.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/internals.h | 2 +-
 target/arm/m_helper.c  | 9 ++++++---
 target/arm/ptw.c       | 9 +++++----
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index f6a9b963d3..30bda00a09 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1113,7 +1113,7 @@ typedef struct V8M_SAttributes {
 
 void v8m_security_lookup(CPUARMState *env, uint32_t address,
                          MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                         V8M_SAttributes *sattrs);
+                         bool secure, V8M_SAttributes *sattrs);
 
 /* Cacheability and shareability attributes for a memory access */
 typedef struct ARMCacheAttrs {
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 01263990dc..45fbf19559 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -689,7 +689,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
         V8M_SAttributes sattrs = {};
 
-        v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
+        v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
+                            targets_secure, &sattrs);
         if (sattrs.ns) {
             attrs.secure = false;
         } else if (!targets_secure) {
@@ -2002,7 +2003,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
     ARMMMUFaultInfo fi = {};
     MemTxResult txres;
 
-    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
+    v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
+                        regime_is_secure(env, mmu_idx), &sattrs);
     if (!sattrs.nsc || sattrs.ns) {
         /*
          * This must be the second half of the insn, and it straddles a
@@ -2826,7 +2828,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     }
 
     if (env->v7m.secure) {
-        v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
+        v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
+                            targetsec, &sattrs);
         nsr = sattrs.ns && r;
         nsrw = sattrs.ns && rw;
     } else {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 5274d0b304..3b70c423a8 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1853,8 +1853,8 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
 }
 
 void v8m_security_lookup(CPUARMState *env, uint32_t address,
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
-                                V8M_SAttributes *sattrs)
+                         MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                         bool is_secure, V8M_SAttributes *sattrs)
 {
     /*
      * Look up the security attributes for this address. Compare the
@@ -1882,7 +1882,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
     }
 
     if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
-        sattrs->ns = !regime_is_secure(env, mmu_idx);
+        sattrs->ns = !is_secure;
         return;
     }
 
@@ -1971,7 +1971,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
     bool ret;
 
     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
-        v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
+        v8m_security_lookup(env, address, access_type, mmu_idx,
+                            secure, &sattrs);
         if (access_type == MMU_INST_FETCH) {
             /*
              * Instruction fetches always use the MMU bank and the
-- 
2.34.1



  parent reply	other threads:[~2022-07-03  8:43 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-03  8:23 [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-03  8:23 ` [PATCH 01/62] accel/tcg: Introduce PageEntryExtra Richard Henderson
2022-07-04 15:28   ` Peter Maydell
2022-07-05  0:35     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 02/62] target/arm: Enable PageEntryExtra Richard Henderson
2022-07-04 15:22   ` Peter Maydell
2022-07-05  1:01     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 03/62] target/arm: Fix MTE check in sve_ldnfff1_r Richard Henderson
2022-07-05 12:05   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page Richard Henderson
2022-07-05 12:09   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 05/62] target/arm: Use PageEntryExtra for MTE Richard Henderson
2022-07-05 12:47   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 06/62] target/arm: Use PageEntryExtra for BTI Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 08/62] target/arm: Create GetPhysAddrResult Richard Henderson
2022-08-10 13:02   ` Alex Bennée
2022-08-19 17:31     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:09   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:11   ` Alex Bennée
2022-07-03  8:23 ` Richard Henderson [this message]
2022-08-10 13:13   ` [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup Alex Bennée
2022-07-03  8:23 ` [PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 22/62] target/arm: Add secure parameter to get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:16   ` Alex Bennée
2022-08-10 15:33     ` Richard Henderson
2022-08-10 18:46       ` Alex Bennée
2022-07-03  8:23 ` [PATCH 23/62] target/arm: Add is_secure parameter to pmsav7_use_background_region Richard Henderson
2022-08-10 13:17   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 24/62] target/arm: Add is_secure parameter to get_phys_addr_lpae Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 25/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 26/62] target/arm: Add is_secure parameter to regime_translation_disabled Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 28/62] target/arm: Split out get_phys_addr_with_secure Richard Henderson
2022-07-03  8:23 ` [PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn Richard Henderson
2022-08-10 13:27   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE Richard Henderson
2022-07-03  8:23 ` [PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write Richard Henderson
2022-07-03  8:23 ` [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes Richard Henderson
2022-07-03  8:23 ` [PATCH 34/62] target/arm: Reorg regime_translation_disabled Richard Henderson
2022-07-03  8:23 ` [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Richard Henderson
2022-07-03  8:23 ` [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate Richard Henderson
2022-07-03  8:23 ` [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate Richard Henderson
2022-07-03  8:23 ` [PATCH 38/62] target/arm: Fix S2 disabled check " Richard Henderson
2022-07-03  8:23 ` [PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb Richard Henderson
2022-07-03  8:23 ` [PATCH 40/62] target/arm: Pass HCR to attribute subroutines Richard Henderson
2022-07-03  8:23 ` [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1 Richard Henderson
2022-07-03  8:23 ` [PATCH 42/62] target/arm: Split out get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} Richard Henderson
2022-07-03  8:24 ` [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Richard Henderson
2022-07-03  8:24 ` [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking Richard Henderson
2022-07-03  8:24 ` [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation Richard Henderson
2022-07-03  8:24 ` [PATCH 48/62] target/arm: Split out get_phys_addr_twostage Richard Henderson
2022-07-03  8:24 ` [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines Richard Henderson
2022-07-03  8:24 ` [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation Richard Henderson
2022-07-03  8:24 ` [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate Richard Henderson
2022-07-03  8:24 ` [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS Richard Henderson
2022-07-03  8:24 ` [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters Richard Henderson
2022-07-03  8:24 ` [PATCH 54/62] target/arm: Split out S1TranslateResult type Richard Henderson
2022-07-03  8:24 ` [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult Richard Henderson
2022-07-03  8:24 ` [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Richard Henderson
2022-07-03  8:24 ` [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate Richard Henderson
2022-07-03  8:24 ` [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 60/62] target/arm: Don't shift attrs " Richard Henderson
2022-07-03  8:24 ` [PATCH 61/62] target/arm: Consider GP an attribute " Richard Henderson
2022-07-03  8:24 ` [PATCH 62/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-04 14:54 ` [PATCH 00/62] " Peter Maydell
2022-07-04 14:58   ` Richard Henderson
2022-07-04 15:57     ` Peter Maydell
2022-08-12 16:31 ` Peter Maydell
2022-08-12 17:54   ` Richard Henderson

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