From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v6 30/45] target/arm: Implement SCLAMP, UCLAMP
Date: Fri, 8 Jul 2022 20:45:25 +0530 [thread overview]
Message-ID: <20220708151540.18136-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org>
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 18 +++++++
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++
target/arm/vec_helper.c | 24 +++++++++
4 files changed, 149 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 3a8ce42ab0..92f36d9dbb 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9e48f07b4..14b3a69c36 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \
@psel esz=2 imm=%psel_imm_s
PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
@psel esz=3 imm=%psel_imm_d
+
+### SVE clamp
+
+SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm
+UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9ed3b267fd..41f8b12259 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7478,3 +7478,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
tcg_temp_free_ptr(ptr);
return true;
}
+
+static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_smax_i32(d, a, n);
+ tcg_gen_smin_i32(d, d, m);
+}
+
+static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_smax_i64(d, a, n);
+ tcg_gen_smin_i64(d, d, m);
+}
+
+static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_smax_vec(vece, d, a, n);
+ tcg_gen_smin_vec(vece, d, d, m);
+}
+
+static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] = {
+ INDEX_op_smin_vec, INDEX_op_smax_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ { .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_b,
+ .opt_opc = vecop,
+ .vece = MO_8 },
+ { .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_h,
+ .opt_opc = vecop,
+ .vece = MO_16 },
+ { .fni4 = gen_sclamp_i32,
+ .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_s,
+ .opt_opc = vecop,
+ .vece = MO_32 },
+ { .fni8 = gen_sclamp_i64,
+ .fniv = gen_sclamp_vec,
+ .fno = gen_helper_gvec_sclamp_d,
+ .opt_opc = vecop,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a)
+
+static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_umax_i32(d, a, n);
+ tcg_gen_umin_i32(d, d, m);
+}
+
+static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_umax_i64(d, a, n);
+ tcg_gen_umin_i64(d, d, m);
+}
+
+static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_umax_vec(vece, d, a, n);
+ tcg_gen_umin_vec(vece, d, d, m);
+}
+
+static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] = {
+ INDEX_op_umin_vec, INDEX_op_umax_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ { .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_b,
+ .opt_opc = vecop,
+ .vece = MO_8 },
+ { .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_h,
+ .opt_opc = vecop,
+ .vece = MO_16 },
+ { .fni4 = gen_uclamp_i32,
+ .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_s,
+ .opt_opc = vecop,
+ .vece = MO_32 },
+ { .fni8 = gen_uclamp_i64,
+ .fniv = gen_uclamp_vec,
+ .fno = gen_helper_gvec_uclamp_d,
+ .opt_opc = vecop,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 9a9c034e36..f59d3b26ea 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+#define DO_CLAMP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
+ TYPE aa = *(TYPE *)(a + i); \
+ TYPE nn = *(TYPE *)(n + i); \
+ TYPE mm = *(TYPE *)(m + i); \
+ TYPE dd = MIN(MAX(aa, nn), mm); \
+ *(TYPE *)(d + i) = dd; \
+ } \
+ clear_tail(d, opr_sz, simd_maxsz(desc)); \
+}
+
+DO_CLAMP(gvec_sclamp_b, int8_t)
+DO_CLAMP(gvec_sclamp_h, int16_t)
+DO_CLAMP(gvec_sclamp_s, int32_t)
+DO_CLAMP(gvec_sclamp_d, int64_t)
+
+DO_CLAMP(gvec_uclamp_b, uint8_t)
+DO_CLAMP(gvec_uclamp_h, uint16_t)
+DO_CLAMP(gvec_uclamp_s, uint32_t)
+DO_CLAMP(gvec_uclamp_d, uint64_t)
--
2.34.1
next prev parent reply other threads:[~2022-07-08 15:48 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-08 15:14 [PATCH v6 00/45] target/arm: Scalable Matrix Extension Richard Henderson
2022-07-08 15:14 ` [PATCH v6 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Richard Henderson
2022-07-08 15:14 ` [PATCH v6 02/45] target/arm: Add infrastructure for disas_sme Richard Henderson
2022-07-08 15:14 ` [PATCH v6 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Richard Henderson
2022-07-08 15:14 ` [PATCH v6 04/45] target/arm: Mark ADR as non-streaming Richard Henderson
2022-07-08 15:15 ` [PATCH v6 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 07/45] target/arm: Mark PMULL, FMMLA " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 10/45] target/arm: Mark string/histo/crypto " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 11/45] target/arm: Mark gather/scatter load/store " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 12/45] target/arm: Mark gather prefetch " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 14/45] target/arm: Mark LD1RO " Richard Henderson
2022-07-08 15:15 ` [PATCH v6 15/45] target/arm: Add SME enablement checks Richard Henderson
2022-07-08 15:15 ` [PATCH v6 16/45] target/arm: Handle SME in sve_access_check Richard Henderson
2022-07-08 15:15 ` [PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Richard Henderson
2022-07-08 15:15 ` [PATCH v6 18/45] target/arm: Implement SME ZERO Richard Henderson
2022-07-08 15:15 ` [PATCH v6 19/45] target/arm: Implement SME MOVA Richard Henderson
2022-07-08 15:15 ` [PATCH v6 20/45] target/arm: Implement SME LD1, ST1 Richard Henderson
2022-07-08 15:15 ` [PATCH v6 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Richard Henderson
2022-07-08 15:15 ` [PATCH v6 22/45] target/arm: Implement SME LDR, STR Richard Henderson
2022-07-08 15:15 ` [PATCH v6 23/45] target/arm: Implement SME ADDHA, ADDVA Richard Henderson
2022-07-08 15:15 ` [PATCH v6 24/45] target/arm: Implement FMOPA, FMOPS (non-widening) Richard Henderson
2022-07-08 15:15 ` [PATCH v6 25/45] target/arm: Implement BFMOPA, BFMOPS Richard Henderson
2022-07-08 15:15 ` [PATCH v6 26/45] target/arm: Implement FMOPA, FMOPS (widening) Richard Henderson
2022-07-08 15:15 ` [PATCH v6 27/45] target/arm: Implement SME integer outer product Richard Henderson
2022-07-08 15:15 ` [PATCH v6 28/45] target/arm: Implement PSEL Richard Henderson
2022-07-08 15:15 ` [PATCH v6 29/45] target/arm: Implement REVD Richard Henderson
2022-07-08 15:15 ` Richard Henderson [this message]
2022-07-08 15:15 ` [PATCH v6 31/45] target/arm: Reset streaming sve state on exception boundaries Richard Henderson
2022-07-08 15:15 ` [PATCH v6 32/45] target/arm: Enable SME for -cpu max Richard Henderson
2022-07-08 15:15 ` [PATCH v6 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Richard Henderson
2022-07-08 15:15 ` [PATCH v6 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Richard Henderson
2022-07-08 15:15 ` [PATCH v6 35/45] linux-user/aarch64: Add SM bit to SVE signal context Richard Henderson
2022-07-08 15:15 ` [PATCH v6 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Richard Henderson
2022-07-08 15:15 ` [PATCH v6 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Richard Henderson
2022-07-08 15:15 ` [PATCH v6 38/45] linux-user/aarch64: Verify extra record lock succeeded Richard Henderson
2022-07-08 15:15 ` [PATCH v6 39/45] linux-user/aarch64: Move sve record checks into restore Richard Henderson
2022-07-08 15:15 ` [PATCH v6 40/45] linux-user/aarch64: Implement SME signal handling Richard Henderson
2022-07-08 15:15 ` [PATCH v6 41/45] linux-user: Rename sve prctls Richard Henderson
2022-07-08 15:15 ` [PATCH v6 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Richard Henderson
2022-07-08 15:15 ` [PATCH v6 43/45] target/arm: Only set ZEN in reset if SVE present Richard Henderson
2022-07-08 15:15 ` [PATCH v6 44/45] target/arm: Enable SME for user-only Richard Henderson
2022-07-08 15:15 ` [PATCH v6 45/45] linux-user/aarch64: Add SME related hwcap entries Richard Henderson
2022-07-11 12:50 ` [PATCH v6 00/45] target/arm: Scalable Matrix Extension Peter Maydell
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