From: Weiwei Li <liweiwei@iscas.ac.cn>
To: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations
Date: Sun, 10 Jul 2022 16:23:55 +0800 [thread overview]
Message-ID: <20220710082400.29224-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220710082400.29224-1-liweiwei@iscas.ac.cn>
- There are 3 suggested privilege modes conbinations listed in the spec:
1) M, 2) M, U 3) M, S, U
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bb3973806..0dad6906bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -636,6 +636,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+ error_setg(errp,
+ "Setting S extension without U extension is illegal");
+ return;
+ }
+
if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
error_setg(errp, "F extension requires Zicsr");
return;
--
2.17.1
next prev parent reply other threads:[~2022-07-10 8:26 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-10 8:23 [PATCH 0/6] Improve the U/S/H extension related check Weiwei Li
2022-07-10 8:23 ` Weiwei Li [this message]
2022-07-11 5:29 ` [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations Alistair Francis
2022-07-10 8:23 ` [PATCH 2/6] target/riscv: H extension depends on I extension Weiwei Li
2022-07-11 5:29 ` Alistair Francis
2022-07-10 8:23 ` [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table Weiwei Li
2022-07-11 6:41 ` Alistair Francis
2022-07-11 12:41 ` Weiwei Li
2022-07-10 8:23 ` [PATCH 4/6] target/riscv: add check for csrs existed with U extension Weiwei Li
2022-07-11 6:42 ` Alistair Francis
2022-07-10 8:23 ` [PATCH 5/6] target/riscv: fix checks in hmode/hmode32 Weiwei Li
2022-07-11 6:46 ` Alistair Francis
2022-07-11 12:45 ` Weiwei Li
2022-07-10 8:24 ` [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check Weiwei Li
2022-07-11 6:49 ` Alistair Francis
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