* [PATCH] target/riscv: move zmmul out of the experimental properties
@ 2022-07-10 10:15 Weiwei Li
2022-07-12 5:17 ` Alistair Francis
2022-07-12 5:36 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Weiwei Li @ 2022-07-10 10:15 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- Zmmul is ratified and is now version 1.0
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bb3973806..6301871fdf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -924,12 +924,13 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+ DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
+
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
- DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: move zmmul out of the experimental properties
2022-07-10 10:15 [PATCH] target/riscv: move zmmul out of the experimental properties Weiwei Li
@ 2022-07-12 5:17 ` Alistair Francis
2022-07-12 5:36 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-07-12 5:17 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
On Sun, Jul 10, 2022 at 8:16 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - Zmmul is ratified and is now version 1.0
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..6301871fdf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -924,12 +924,13 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
>
> + DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
> +
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
>
> /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> - DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: move zmmul out of the experimental properties
2022-07-10 10:15 [PATCH] target/riscv: move zmmul out of the experimental properties Weiwei Li
2022-07-12 5:17 ` Alistair Francis
@ 2022-07-12 5:36 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-07-12 5:36 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
On Sun, Jul 10, 2022 at 8:16 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - Zmmul is ratified and is now version 1.0
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..6301871fdf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -924,12 +924,13 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
>
> + DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
> +
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
>
> /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> - DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-07-10 10:15 [PATCH] target/riscv: move zmmul out of the experimental properties Weiwei Li
2022-07-12 5:17 ` Alistair Francis
2022-07-12 5:36 ` Alistair Francis
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