From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Iris Chen" <irischenlj@fb.com>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 16/19] hw: m25p80: add tests for BP and TB bit write protect
Date: Wed, 13 Jul 2022 09:52:52 +0200 [thread overview]
Message-ID: <20220713075255.2248923-17-clg@kaod.org> (raw)
In-Reply-To: <20220713075255.2248923-1-clg@kaod.org>
From: Iris Chen <irischenlj@fb.com>
Signed-off-by: Iris Chen <irischenlj@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627185234.1911337-3-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/qtest/aspeed_smc-test.c | 111 ++++++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 1258687eacd8..05ce941566e6 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -192,6 +192,24 @@ static void read_page_mem(uint32_t addr, uint32_t *page)
}
}
+static void write_page_mem(uint32_t addr, uint32_t write_value)
+{
+ spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+
+ for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
+ }
+}
+
+static void assert_page_mem(uint32_t addr, uint32_t expected_value)
+{
+ uint32_t page[FLASH_PAGE_SIZE / 4];
+ read_page_mem(addr, page);
+ for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+ g_assert_cmphex(page[i], ==, expected_value);
+ }
+}
+
static void test_erase_sector(void)
{
uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
@@ -501,6 +519,95 @@ static void test_status_reg_write_protection(void)
flash_reset();
}
+static void test_write_block_protect(void)
+{
+ uint32_t sector_size = 65536;
+ uint32_t n_sectors = 512;
+
+ spi_ce_ctrl(1 << CRTL_EXTENDED0);
+ spi_conf(CONF_ENABLE_W0);
+
+ uint32_t bp_bits = 0b0;
+
+ for (int i = 0; i < 16; i++) {
+ bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
+
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ writeb(ASPEED_FLASH_BASE, BULK_ERASE);
+ writeb(ASPEED_FLASH_BASE, WREN);
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, bp_bits);
+ writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+ writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_stop_user();
+
+ uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+ uint32_t protection_start = n_sectors - num_protected_sectors;
+ uint32_t protection_end = n_sectors;
+
+ for (int sector = 0; sector < n_sectors; sector++) {
+ uint32_t addr = sector * sector_size;
+
+ assert_page_mem(addr, 0xffffffff);
+ write_page_mem(addr, make_be32(0xabcdef12));
+
+ uint32_t expected_value = protection_start <= sector
+ && sector < protection_end
+ ? 0xffffffff : 0xabcdef12;
+
+ assert_page_mem(addr, expected_value);
+ }
+ }
+
+ flash_reset();
+}
+
+static void test_write_block_protect_bottom_bit(void)
+{
+ uint32_t sector_size = 65536;
+ uint32_t n_sectors = 512;
+
+ spi_ce_ctrl(1 << CRTL_EXTENDED0);
+ spi_conf(CONF_ENABLE_W0);
+
+ /* top bottom bit is enabled */
+ uint32_t bp_bits = 0b00100 << 3;
+
+ for (int i = 0; i < 16; i++) {
+ bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
+
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ writeb(ASPEED_FLASH_BASE, BULK_ERASE);
+ writeb(ASPEED_FLASH_BASE, WREN);
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, bp_bits);
+ writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+ writeb(ASPEED_FLASH_BASE, WREN);
+ spi_ctrl_stop_user();
+
+ uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+ uint32_t protection_start = 0;
+ uint32_t protection_end = num_protected_sectors;
+
+ for (int sector = 0; sector < n_sectors; sector++) {
+ uint32_t addr = sector * sector_size;
+
+ assert_page_mem(addr, 0xffffffff);
+ write_page_mem(addr, make_be32(0xabcdef12));
+
+ uint32_t expected_value = protection_start <= sector
+ && sector < protection_end
+ ? 0xffffffff : 0xabcdef12;
+
+ assert_page_mem(addr, expected_value);
+ }
+ }
+
+ flash_reset();
+}
+
static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
int main(int argc, char **argv)
@@ -529,6 +636,10 @@ int main(int argc, char **argv)
qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
qtest_add_func("/ast2400/smc/status_reg_write_protection",
test_status_reg_write_protection);
+ qtest_add_func("/ast2400/smc/write_block_protect",
+ test_write_block_protect);
+ qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
+ test_write_block_protect_bottom_bit);
flash_reset();
ret = g_test_run();
--
2.35.3
next prev parent reply other threads:[~2022-07-13 8:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 7:52 [PULL 00/19] aspeed queue Cédric Le Goater
2022-07-13 7:52 ` [PULL 01/19] aspeed: sbc: Allow per-machine settings Cédric Le Goater
2022-07-13 7:52 ` [PULL 02/19] hw/i2c/pmbus: Add idle state to return 0xff's Cédric Le Goater
2022-07-13 7:52 ` [PULL 03/19] hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators Cédric Le Goater
2022-07-13 7:52 ` [PULL 04/19] hw/sensor: Add Renesas ISL69259 device model Cédric Le Goater
2022-07-13 7:52 ` [PULL 05/19] aspeed: Create SRAM name from first CPU index Cédric Le Goater
2022-07-13 7:52 ` [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines Cédric Le Goater
2022-07-13 7:52 ` [PULL 07/19] aspeed: Make aspeed_board_init_flashes public Cédric Le Goater
2022-07-13 7:52 ` [PULL 08/19] aspeed: Add fby35 skeleton Cédric Le Goater
2022-07-13 7:52 ` [PULL 09/19] aspeed: Add AST2600 (BMC) to fby35 Cédric Le Goater
2022-07-13 7:52 ` [PULL 10/19] aspeed: fby35: Add a bootrom for the BMC Cédric Le Goater
2022-07-13 7:52 ` [PULL 11/19] aspeed: Add AST1030 (BIC) to fby35 Cédric Le Goater
2022-07-13 7:52 ` [PULL 12/19] docs: aspeed: Add fby35 multi-SoC machine section Cédric Le Goater
2022-07-13 7:52 ` [PULL 13/19] docs: aspeed: Minor updates Cédric Le Goater
2022-07-13 7:52 ` [PULL 14/19] test/avocado/machine_aspeed.py: Add SDK tests Cédric Le Goater
2022-07-13 7:52 ` [PULL 15/19] hw: m25p80: Add Block Protect and Top Bottom bits for write protect Cédric Le Goater
2022-07-13 7:52 ` Cédric Le Goater [this message]
2022-07-13 7:52 ` [PULL 17/19] qtest/aspeed_gpio: Add input pin modification test Cédric Le Goater
2022-07-13 7:52 ` [PULL 18/19] hw/gpio/aspeed: Don't let guests modify input pins Cédric Le Goater
2022-07-13 7:52 ` [PULL 19/19] aspeed: Add fby35-bmc slot GPIO's Cédric Le Goater
2022-07-14 13:51 ` [PULL 00/19] aspeed queue Peter Maydell
2022-07-14 14:26 ` Cédric Le Goater
-- strict thread matches above, loose matches on Subject: below --
2022-07-14 15:44 [PULL v2 " Cédric Le Goater
2022-07-14 15:44 ` [PULL 16/19] hw: m25p80: add tests for BP and TB bit write protect Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220713075255.2248923-17-clg@kaod.org \
--to=clg@kaod.org \
--cc=irischenlj@fb.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).